main.plg

来自「基于FPGA的VHDL编程实现各种音频信号」· PLG 代码 · 共 31 行

@P:  Worst Slack : 1.029
@P:  key_measure|cnt_inferred_clock[16] - Estimated Frequency : 775.9 MHz
@P:  key_measure|cnt_inferred_clock[16] - Requested Frequency : 100.0 MHz
@P:  key_measure|cnt_inferred_clock[16] - Estimated Period : 1.289
@P:  key_measure|cnt_inferred_clock[16] - Requested Period : 10.000
@P:  key_measure|cnt_inferred_clock[16] - Slack : 8.711
@P:  key_measure|key_done_inferred_clock - Estimated Frequency : 243.6 MHz
@P:  key_measure|key_done_inferred_clock - Requested Frequency : 100.0 MHz
@P:  key_measure|key_done_inferred_clock - Estimated Period : 4.105
@P:  key_measure|key_done_inferred_clock - Requested Period : 10.000
@P:  key_measure|key_done_inferred_clock - Slack : 5.895
@P:  main|PLL_25M_U0.clk_25m_inferred_clock - Estimated Frequency : 111.5 MHz
@P:  main|PLL_25M_U0.clk_25m_inferred_clock - Requested Frequency : 100.0 MHz
@P:  main|PLL_25M_U0.clk_25m_inferred_clock - Estimated Period : 8.971
@P:  main|PLL_25M_U0.clk_25m_inferred_clock - Requested Period : 10.000
@P:  main|PLL_25M_U0.clk_25m_inferred_clock - Slack : 1.029
@P:  Total Area : 1050.0
@P:  Total Area : 186.0
@P:  Total Area : 145.0
@P:  Total Area : 197.0
@P:  Total Area : 8.0
@P:  Total Area : 146.0
@P:  Total Area : 66.0
@P:  Total Area : 72.0
@P:  Total Area : 75.0
@P:  Total Area : 46.0
@P:  Total Area : 91.0
@P:  Total Area : 0.0
@P:  Total Area : 1050.0
@P:  CPU Time : 0h:00m:06s