pulse.v

FPGA通信与软件无线电应用高级培训资料

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    01:38:05 05/20/07
// Design Name:    
// Module Name:    pulse
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module pulse(clk,d,fout,cout,cnt2);
input clk;
input[7:0] d;
output fout,cout,cnt2;
reg[8:0] cnt8=9'b100000000;
reg fout="0";
reg cnt2="0";
reg full,cout;
always @(posedge clk)
begin
if(cnt8==9'b100000000)
   begin cnt8=d;
	      full=1'b1;
   end
else 
   begin
	cnt8=cnt8+1;
	full=1'b0;
   end
	cout=full;
end
always @(posedge full)
begin
cnt2=~cnt2;
if(cnt2==1'b1) fout=1'b1;
else fout=1'b0;
end
endmodule