pipsub.v

FPGA通信与软件无线电应用高级培训资料

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:00:18 05/26/07
// Design Name:    
// Module Name:    pipsub
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module pipsub(clk,shifto,rdy,subout);
input clk,rdy;
input[15:0] shifto;
output[15:0] subout;

reg[15:0] subout="0000000000000000";
reg[15:0] subout1="0000000000000000";
reg muls;
reg cout="0";
always@ (posedge clk)
begin
if(rdy==1'b1) begin
if(cout==1'b0) begin
cout<=1'b1;
subout1<=shifto-16'h00ff;
end
else begin
subout<=subout1&16'h00ff;
cout<=1'b0;
end
end
end


endmodule