da.v

来自「FPGA通信与软件无线电应用高级培训资料」· Verilog 代码 · 共 59 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:19:14 05/18/2008 
// Design Name: 
// Module Name:    da 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module da(clk, x_in, y); //----> Interface

  input         clk;
  input  [3:0]  x_in;
  output [6:0]  y;
  reg    [6:0]  y;

  reg  [2:0] x0, x1, x2, x3;
  wire [3:0] y0, y1, y2, y3;
  reg  [4:0] s0, s1;
  reg  [3:0] t0, t1, t2, t3;
  reg  [6:0] y01,y23;

  always @(posedge clk)  
  begin : DA 
    integer k;
    for (k=0; k<=1; k=k+1) begin     
       x0[k] <= x0[k+1];
       x1[k] <= x1[k+1];
       x2[k] <= x2[k+1];
       x3[k] <= x3[k+1];
    end
    x0[2] <= x_in[0];     
    x1[2] <= x_in[1];    
    x2[2] <= x_in[2];
    x3[2] <= x_in[3];
    y01 <= {{3{y0[3]}},y0} + {{2{y1[3]}},y1,1'b0};
    y23 <= {y2[3],y2,2'b00} - (y3 << 3);
    y <= y01 + y23; 

  end

  dafir LC_Table0 ( .table_in(x0), .table_out(y0));
  dafir LC_Table1 ( .table_in(x1), .table_out(y1));
  dafir LC_Table2 ( .table_in(x2), .table_out(y2));
  dafir LC_Table3 ( .table_in(x3), .table_out(y3));

endmodule