dafir.v

FPGA通信与软件无线电应用高级培训资料

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:19:42 05/18/2008 
// Design Name: 
// Module Name:    dafir 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module dafir(table_in, table_out);

  input  [2:0] table_in;   
  output [3:0] table_out; 

  reg [3:0] table_out;

 

  always @(table_in)
  begin
    case (table_in)
      0 :     table_out =  0;
      1 :     table_out =  -2;
      2 :     table_out =  3;
      3 :     table_out =  1;
      4 :     table_out =  1;
      5 :     table_out =  -1;
      6 :     table_out =  4;
      7 :     table_out =  2;
      default : ;
    endcase
  end

endmodule