fpga_led.fit.rpt

点亮数码管，检验开发板的好坏的源代码

; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
; |fpga_led                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 2    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |fpga_led           ; work         ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------+
; Delay Chain Summary                                                           ;
+------+----------+---------------+---------------+-----------------------+-----+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+------+----------+---------------+---------------+-----------------------+-----+
; led1 ; Output   ; --            ; --            ; --                    ; --  ;
; key1 ; Input    ; 6             ; 6             ; --                    ; --  ;
+------+----------+---------------+---------------+-----------------------+-----+


+---------------------------------------------------+
; Pad To Core Delay Chain Fanout                    ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; key1                ;                   ;         ;
;      - led1         ; 0                 ; 6       ;
+---------------------+-------------------+---------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+------+--------------------------+
; Name ; Fan-Out                  ;
+------+--------------------------+
; key1 ; 1                        ;
+------+--------------------------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; Block interconnects        ; 1 / 15,666 ( < 1 % ) ;
; C16 interconnects          ; 1 / 812 ( < 1 % )    ;
; C4 interconnects           ; 1 / 11,424 ( < 1 % ) ;
; Direct links               ; 0 / 15,666 ( 0 % )   ;
; Global clocks              ; 0 / 8 ( 0 % )        ;
; Local interconnects        ; 0 / 4,608 ( 0 % )    ;
; R24 interconnects          ; 1 / 652 ( < 1 % )    ;
; R4 interconnects           ; 0 / 13,328 ( 0 % )   ;
+----------------------------+----------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; nCEO                                         ; Unreserved          ;
; ASDO,nCSO                                    ; As input tri-stated ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 癈   ;
; High Junction Temperature ; 85 癈  ;
+---------------------------+--------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                         ;
+------------------------------------------------------------------+------------+
; Name                                                             ; Value      ;
+------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1                                 ; ff         ;
; Mid Wire Use - Fit Attempt 1                                     ; 0          ;
; Mid Slack - Fit Attempt 1                                        ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1                              ; 0          ;
; LE/ALM Count - Fit Attempt 1                                     ; 0          ;
; LAB Count - Fit Attempt 1                                        ; 0          ;
; Outputs per Lab - Fit Attempt 1                                  ; -1.#IO     ;
; Inputs per LAB - Fit Attempt 1                                   ; -1.#IO     ;
; Global Inputs per LAB - Fit Attempt 1                            ; -1.#IO     ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1    ;            ;
; LAB Constraint 'non-global controls' - Fit Attempt 1             ;            ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1               ;            ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1       ;            ;
; LAB Constraint 'global controls' - Fit Attempt 1                 ;            ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ;            ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ;            ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1      ;            ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1                 ;            ;
;