📄 fpga_yuv2rgb.tdf
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TV_H_START_l_ADDR = (EXTLA[10..0]==B"01000011001"); --50c8
TV_H_END_h_ADDR = (EXTLA[10..0]==B"01000011010"); --50d0
TV_H_END_l_ADDR = (EXTLA[10..0]==B"01000011011"); --50d8
TV_V_START_h_ADDR = (EXTLA[10..0]==B"01000011100"); --50e0
TV_V_START_l_ADDR = (EXTLA[10..0]==B"01000011101"); --50e8
TV_V_END_h_ADDR = (EXTLA[10..0]==B"01000011110"); --50f0
TV_V_END_l_ADDR = (EXTLA[10..0]==B"01000011111"); --50f8
%
av_ram_test_l_addr = (EXTLA[10..0]==B"01000100000"); --5100
av_ram_test_h_addr = (EXTLA[10..0]==B"01000100001"); --5108 --bit0 直通 1:rambuffer 2:SRdataa 3:最终计算得出的数据 4:输入数据测试线
av_ram_test_d_addr = (EXTLA[10..0]==B"01000100010"); --5110 --低4位为水平缩放系数,高4位为垂直缩放系数
--**************************************--
--********** REGISTER CONTROL **********--
----rgb640 index low register 4020
640_index_l_reg[7..0].d = lbmd[47..40];
640_index_l_reg[7..0].ena = 640_index_l_addr;
640_index_l_reg[7..0].clk = fwr_;
----rgb640 index high register 4028
640_index_h_reg[7..0].d = lbmd[47..40];
640_index_h_reg[7..0].ena = 640_index_h_addr;
640_index_h_reg[7..0].clk = fwr_;
---- write rgb640 index h"012c"
640_index_012c_addr =(640_index_l_reg[7..0].q ==h"2c")
&(640_index_h_reg[7..0].q ==h"01")
& 640_index_data_addr
;
640_index_012c_data[7..0] =h"03";
%
--x coordinates of window top left corner; REG ADDRESS 5000-H,5008-L
WIN_X_O_H[7..0].D = LBMD[47..40];
WIN_X_O_H[7..0].ENA = WIN_X_O_H_ADDR;
WIN_X_O_H[7..0].CLK = FWR_;
win_x_o_h_value[7..0] = WIN_X_O_h[7..0].q;
WIN_X_O_L[2].D = LBMD[42];
WIN_X_O_L[2].ENA = WIN_X_O_L_ADDR;
WIN_X_O_L[2].CLK = FWR_;
win_x_o_l_value[1..0] = gnd;
win_x_o_l_value[2] = WIN_X_O_L[2].q;
win_x_o_l_value[7..3] = gnd;
--Y coordiantes of window top left corner; reg address 5010-H, 5018-L
WIN_Y_O_H[7..0].D = LBMD[47..40];
WIN_Y_O_H[7..0].ENA = WIN_Y_O_H_ADDR;
WIN_Y_O_H[7..0].CLK = FWR_;
win_y_o_h_value[7..0] = WIN_y_O_h[7..0].q;
WIN_Y_O_L[2..0].D = LBMD[42..40];
WIN_Y_O_L[2..0].ENA = WIN_Y_O_L_ADDR;
WIN_Y_O_L[2..0].CLK = FWR_;
win_y_o_l_value[2..0] = WIN_y_O_L[2..0].q;
win_y_o_l_value[7..3] = gnd;
--SIGNAL SWITCH ; reg address 5020 BIT0: IF # = 0 ,SHUT DOWN SIGNAL SOURCE
SIGNAL_SWITCH[0].D = LBMD[40];
SIGNAL_SWITCH[0].ENA = SIGNAL_SWITCH_ADDR;
SIGNAL_SWITCH[0].CLK = FWR_;
SIGNAL_SWITCH_value[0] = SIGNAL_SWITCH[0].q;
SIGNAL_SWITCH_value[7..1] = gnd;
--REG ADDRESS 5028 BIT 0: IF # = 0 THEN 512X480 ELSE 412X360
WIN_RESOLUTION[0].D = LBMD[40];
WIN_RESOLUTION[0].ENA = WIN_RESOLUTION_ADDR;
WIN_RESOLUTION[0].CLK = FWR_;
WIN_RESOLUTION_value[0] = WIN_RESOLUTION[0].q;
WIN_RESOLUTION_value[7..1] = gnd;
--SIX SCREEN OF A_DISPLAY ENABLE; REG ADDRESS 5030
A_DISPLAY[5..0].D = LBMD[45..40];
A_DISPLAY[5..0].ENA = A_DISPLAY_ADDR;
A_DISPLAY[5..0].CLK = FWR_;
A_DISPLAY[5..0].prn = resetn;
A_DISPLAY_value[5..0] = A_DISPLAY[5..0].q;
A_DISPLAY_value[7..6] = gnd;
--FREEZE DISPLAY; REG ADDRESS 5038 BIT0: IF # = 0 , NORMAL OPERATION, ELSE FREEZE DISPLAY
a_freeze[0].D = LBMD[40];
a_freeze[0].ENA = a_freeze_addr;
a_freeze[0].CLK = FWR_;
--a_freeze[0].clrn =!(fvsync_count_1800.q[10..0]==h"708");
a_freeze_value[0] = a_freeze[0].q;
a_freeze_value[7..1] = gnd;
--WAVE GATE WIDTH; REG ADDRESS 5040
W_G_WIDTH[2..0].D = LBMD[42..40];
W_G_WIDTH[2..0].ENA = W_G_WIDTH_ADDR;
W_G_WIDTH[2..0].CLK = FWR_;
W_G_WIDTH[7..5].D = LBMD[47..45];
W_G_WIDTH[7..5].ENA = W_G_WIDTH_ADDR;
W_G_WIDTH[7..5].CLK = FWR_;
W_G_WIDTH_value[2..0] = W_G_WIDTH[2..0].q;
W_G_WIDTH_value[4..3] = gnd;
W_G_WIDTH_value[7..5] = W_G_WIDTH[7..5].q;
--WAVE GATE DEPTH; REG ADDRESS 5048
W_G_DEPTH[1..0].D = LBMD[41..40];
W_G_DEPTH[1..0].ENA = W_G_DEPTH_ADDR;
W_G_DEPTH[1..0].CLK = FWR_;
W_G_DEPTH_value[1..0] = W_G_DEPTH[1..0].q;
W_G_DEPTH_value[7..2] = gnd;
%
--I2C DATA LINE; REG ADDRESS 5050 BIT 0
SDAREG[0].D = LBMD[40];
SDAREG[0].ENA = SDA_ADDR;
SDAREG[0].CLK = FWR_;
SDAREG_value[0] = iicsda; --SDAREG[0].q;
SDAREG_value[7..1] = gnd;
--I2C CLOCK LINE; REG ADDRESS 5058 BIT 0
SCLREG[0].D = LBMD[40];
SCLREG[0].ENA = SCL_ADDR;
SCLREG[0].CLK = FWR_;
SCLREG_value[0] = SCLREG[0].q;
SCLREG_value[7..1] = gnd;
--AV_WINDOW & TV_WINDOW PRI; REG ADDRESS 5060 BIT 0
PRI[0].D = LBMD[40];
PRI[0].ENA = PRI_ADDR;
PRI[0].CLK = FWR_;
PRI_value[0] = PRI[0].q;
PRI_value[7..1] = gnd;
%
----OC GATE OUTPUT REGISTER; REG ADDRESS 5080
--U65 OUTPUT [7..0];
OC_OUT_CTL[7..0].D = LBMD[47..40];
OC_OUT_CTL[7..0].ENA = OC_OUT_CTL_ADDR;
OC_OUT_CTL[7..0].CLK = FWR_;
OC_OUT_CTL[7..0].prn = resetn;
OC_OUT_CTL_value[7..0] = OC_OUT_CTL[7..0].q;
----TTL INPUT u66=7..0; REG ADDRESS 5090 (READ ONLY)
--u66 input [7..0]
TTL_IN_CTL_value[7..0] =(id==1)& gnd
& gnd
;
TTL_IN_CTL_value[6..0] =(id==1)& OC_TTL[6..0]
;
----SWITCH INPUT u65=3..0;u66=7..4; REG ADDRESS 50A0 (READ ONLY)
SW_IN_CTL_value[3..0] =(id==0)& K0[3..0];
SW_IN_CTL_value[7..4] =(id==1)& K0[3..0];
----SELF TEST REGISTER; REF ADDRESS 50B0 (READ ONLY)
SELF_TEST_value[7..4] = h"5";
SELF_TEST_value[3] = gnd;--arblk_value;
SELF_TEST_value[2] = gnd;--addl_value;
SELF_TEST_value[1] = gnd;--arcf_value;
SELF_TEST_value[0] = gnd;--arad_value;
%
%
----tv ctl REGISTER; REF ADDRESS 50B0
tv_ctl[0].D = LBMD[40];
tv_ctl[0].ENA = tv_ctl_addr;
tv_ctl[0].CLK = FWR_;
tv_ctl[4].D = LBMD[44];
tv_ctl[4].ENA = tv_ctl_addr;
tv_ctl[4].CLK = FWR_;
tv_ctl_value[0] = tv_ctl[0].q;
tv_ctl_value[3..1] = gnd;
tv_ctl_value[4] = tv_ctl[4].q;
tv_ctl_value[7..5] = gnd;
----TV WINDOW H POSITION START REGISTER; REF ADDRESS 50C0-h
TV_H_START_H[7..0].D = LBMD[47..40];
TV_H_START_H[7..0].ENA = TV_H_START_H_ADDR;
TV_H_START_H[7..0].CLK = FWR_;
----TV WINDOW H POSITION START REGISTER; REF ADDRESS 50C8-l
TV_H_START_L[2..0].D = LBMD[42..40];
TV_H_START_L[2..0].ENA = TV_H_START_L_ADDR;
TV_H_START_L[2..0].CLK = FWR_;
tv_h_start_l_value[2..0]= TV_H_START_L[2..0].q;
tv_h_start_l_value[7..3]= gnd;
----TV WINDOW H POSITION END REGISTER; REF ADDRESS 50D0-H
TV_H_END_H[7..0].D = LBMD[47..40];
TV_H_END_H[7..0].ENA = TV_h_end_H_ADDR;
TV_H_END_H[7..0].CLK = FWR_;
----TV WINDOW H POSITION END REGISTER; REF ADDRESS 50D8-L
TV_H_END_L[2..0].D = LBMD[42..40];
TV_H_END_L[2..0].ENA = TV_h_end_L_ADDR;
TV_H_END_L[2..0].CLK = FWR_;
tv_h_end_l_value[2..0] = tv_h_end_l[2..0].q;
tv_h_end_l_value[7..3] = gnd;
----TV WINDOW V POSITION START REGISTER; REF ADDRESS 50E0-h
TV_V_START_H[7..0].D = LBMD[47..40];
TV_V_START_H[7..0].ENA = TV_V_START_H_ADDR;
TV_V_START_H[7..0].CLK = FWR_;
----TV WINDOW V POSITION START REGISTER; REF ADDRESS 50E8-l
TV_V_START_L[2..0].D = LBMD[42..40];
TV_V_START_L[2..0].ENA = TV_V_START_L_ADDR;
TV_V_START_L[2..0].CLK = FWR_;
tv_v_start_l_value[2..0] = tv_v_start_l[2..0].q;
tv_v_start_l_value[7..3] = gnd;
----TV WINDOW V POSITION END REGISTER; REF ADDRESS 50F0-H
TV_V_END_H[7..0].D = LBMD[47..40];
TV_V_END_H[7..0].ENA = TV_V_end_H_ADDR;
TV_V_END_H[7..0].CLK = FWR_;
----TV WINDOW V POSITION END REGISTER; REF ADDRESS 50F8-L
TV_V_END_L[2..0].D = LBMD[42..40];
TV_V_END_L[2..0].ENA = TV_v_end_L_ADDR;
TV_V_END_L[2..0].CLK = FWR_;
tv_v_end_l_value[2..0] = tv_v_end_l[2..0].q;
tv_v_end_l_value[7..3] = gnd;
%
----av test register 5100
av_ram_test_l[7..0].d = lbmd[47..40];
av_ram_test_h[7..0].d = lbmd[47..40];
av_ram_test_d[7..0].d = lbmd[47..40];
av_ram_test_l[7..0].ena = av_ram_test_l_addr;
av_ram_test_h[7..0].ena = av_ram_test_h_addr;
av_ram_test_d[7..0].ena = av_ram_test_d_addr;
av_ram_test_l[7..0].clk = fwr_;
av_ram_test_h[7..0].clk = fwr_;
av_ram_test_d[7..0].clk = fwr_;
test_ts = av_ram_test_h[6].q;
test_ms = av_ram_test_h[5].q;
test_ka/ku = av_ram_test_h[4].q;
test_wram_addr[7..0] = av_ram_test_l[7..0].q;
test_wram_addr[11..8] = av_ram_test_h[3..0].q;
--*****************************************--
--********** GLINT READ REGISTER **********--
fRD_DELAY_reg[0].d = FRD_;
fRD_DELAY_reg[1].d = fRD_DELAY_reg[0].q;
fRD_DELAY_reg[1..0].clk = gmclk;
fwr_DELAY_reg[0].d = Fwr_;
fwr_DELAY_reg[1].d = fwr_DELAY_reg[0].q;
fwr_DELAY_reg[1..0].clk = gmclk;
LDA_TRI[7..0].OE = -- !fwr_DELAY_reg[1].q & 640_index_012c_addr & h"0e" --0430 & 640index=012c
%
(ID==0)&!fRD_DELAY_reg[1].q & WIN_X_O_H_ADDR --5000
#(ID==0)&!fRD_DELAY_reg[1].q & WIN_X_O_L_ADDR --5008
#(ID==0)&!fRD_DELAY_reg[1].q & WIN_Y_O_H_ADDR --5010
#(ID==0)&!fRD_DELAY_reg[1].q & WIN_Y_O_L_ADDR --5018
#(ID==0)&!fRD_DELAY_reg[1].q & SIGNAL_SWITCH_ADDR --5020 -- BIT 0
#(ID==0)&!fRD_DELAY_reg[1].q & WIN_RESOLUTION_ADDR --5028 -- BIT 0
#(ID==0)&!fRD_DELAY_reg[1].q & A_DISPLAY_ADDR --5030
#(ID==0)&!fRD_DELAY_reg[1].q & a_freeze_ADDR --5038
#(ID==0)&!fRD_DELAY_reg[1].q & W_G_WIDTH_ADDR --5040
#(ID==0)&!fRD_DELAY_reg[1].q & W_G_DEPTH_ADDR --5048
%
% #%(ID==0)&!fRD_DELAY_reg[1].q & SDA_ADDR --5050
#(ID==0)&!fRD_DELAY_reg[1].q & SCL_ADDR --5058
#(ID==0)&!fRD_DELAY_reg[1].q & PRI_ADDR --5060
%
#(ID==0)&!fRD_DELAY_reg[1].q & OC_OUT_CTL_ADDR --5080
#(id==1)&!fRD_DELAY_reg[1].q & TTL_IN_CTL_ADDR --5090
#(id==0)&!fRD_DELAY_reg[1].q & SW_IN_CTL_ADDR & h"0f" --50a0
#(id==1)&!fRD_DELAY_reg[1].q & SW_IN_CTL_ADDR & h"f0" --50a0
#(ID==0)&!fRD_DELAY_reg[1].q & SELF_TEST_ADDR --50b0
%
%
#(ID==0)&!fRD_DELAY_reg[1].q & tv_ctl_addr --50b8
#(ID==0)&!fRD_DELAY_reg[1].q & TV_H_START_H_ADDR --50c0
#(ID==0)&!fRD_DELAY_reg[1].q & TV_H_START_L_ADDR --50c8
#(ID==0)&!fRD_DELAY_reg[1].q & TV_H_END_H_ADDR --50d0
#(ID==0)&!fRD_DELAY_reg[1].q & TV_H_END_L_ADDR --50d8
#(ID==0)&!fRD_DELAY_reg[1].q & TV_V_START_H_ADDR --50e0
#(ID==0)&!fRD_DELAY_reg[1].q & TV_V_START_L_ADDR --50e8
#(ID==0)&!fRD_DELAY_reg[1].q & TV_V_END_H_ADDR --50f0
#(ID==0)&!fRD_DELAY_reg[1].q & TV_V_END_L_ADDR --50f8
%
#(ID==0)&!fRD_DELAY_reg[1].q & av_ram_test_l_addr --5100
#(ID==0)&!fRD_DELAY_reg[1].q & av_ram_test_h_addr --5108
#(ID==0)&!fRD_DELAY_reg[1].q & av_ram_test_d_addr --5110
;
LDA_TRI[7..0].IN = -- 640_index_012c_data[7..0] & 640_index_012c_addr --0430 & 640index=012c
%
# WIN_X_O_H_value[7..0] & WIN_X_O_H_ADDR --5000
# WIN_X_O_L_value[7..0] & WIN_X_O_L_ADDR --5008 3bit
# WIN_Y_O_H_VALUE[7..0] & WIN_Y_O_H_ADDR --5010
# WIN_Y_O_L_value[7..0] & WIN_Y_O_L_ADDR --5018
# SIGNAL_SWITCH_value[7..0] & SIGNAL_SWITCH_ADDR --5020
# WIN_RESOLUTION_value[7..0] & WIN_RESOLUTION_ADDR --5028
# A_DISPLAY_value[7..0] & A_DISPLAY_ADDR --5030
# a_freeze_value[7..0] & a_freeze_ADDR --5038
# W_G_WIDTH_value[7..0] & W_G_WIDTH_ADDR --5040
# W_G_DEPTH_value[7..0] & W_G_DEPTH_ADDR --5048
%
%#% SDAREG_value[7..0] & SDA_ADDR --5050
# SCLREG_value[7..0] & SCL_ADDR --5058
# PRI_value[7..0] & PRI_ADDR --5060
%
# OC_OUT_CTL_value[7..0] & OC_OUT_CTL_ADDR --5080
# TTL_IN_CTL_value[7..0] & TTL_IN_CTL_ADDR --5090
# SW_IN_CTL_value[7..0] & SW_IN_CTL_ADDR --50a0
# SELF_TEST_value[7..0] & SELF_TEST_ADDR --50b0
%
%
# tv_ctl_value[7..0] & tv_ctl_addr --50b8
# TV_H_START_H[7..0].Q& TV_H_START_H_ADDR --50c0
# TV_H_START_L_value[7..0] & TV_H_START_L_ADDR --50c8
# TV_H_END_H[7..0].Q& TV_H_END_H_ADDR --50d0
# TV_H_END_L_value[7..0] & TV_H_END_L_ADDR --50d8
# TV_V_START_H[7..0].Q& TV_V_START_H_ADDR --50e0
# TV_V_START_L_value[7..0] & TV_V_START_L_ADDR --50e8
# TV_V_END_H[7..0].Q& TV_V_END_H_ADDR --50f0
# TV_V_END_L_value[7..0] & TV_V_END_L_ADDR --50f8
%
# av_ram_test_l[7..0].q & av_ram_test_l_addr --5100
# av_ram_test_h[7..0].q & av_ram_test_h_addr --5108
# av_ram_test_d[7..0].q & av_ram_test_d_addr --5110
;
LBMD[47..40] = LDA_TRI[7..0].OUT;
--**************************************************************--
--**************************************************************--
----*************************************************************
----******************** STORE ad input DATA *********************
----**************************************************************
-------------------------------------------------------------------
-- n_count.q =8 n 计数值限制，m的翻转次数
-- m_value_reg 0,1,0,1,0,1,0,1,0；m=0⌨️ 快捷键说明
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