📄 fpga_yuv2rgb.tdf
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--RAM输出数据
SRdataa[7..0].d = rambuffer[0].q[7..0]&(ram_readaddr[9]==1) --& rd_disp_en ----y0 y1
--# rambuffer[1].q[7..0]&(rdaddr_reg[1][1..0].q==1) --& rd_disp_en
# rambuffer[2].q[7..0]&(ram_readaddr[9]==0) --& rd_disp_en
--# rambuffer[3].q[7..0]&(rdaddr_reg[1][1..0].q==3) --& rd_disp_en
;
SRdatab[7..0].d = rambuffer[1].q[7..0]&(ram_readaddr[9]==1) --& rd_disp_en ----cr cb
--# rambuffer[0].q[7..0]&(rdaddr_reg[1][1..0].q==1) --& rd_disp_en
# rambuffer[3].q[7..0]&(ram_readaddr[9]==0) --& rd_disp_en
--# rambuffer[2].q[7..0]&(rdaddr_reg[1][1..0].q==3) --& rd_disp_en
;
%
SRdatac[7..0].d = rambuffer[2].q[7..0]&(rdaddr_reg[1][1..0].q==0) --& rd_disp_en
# rambuffer[3].q[7..0]&(rdaddr_reg[1][1..0].q==1) --& rd_disp_en
# rambuffer[0].q[7..0]&(rdaddr_reg[1][1..0].q==2) --& rd_disp_en
# rambuffer[1].q[7..0]&(rdaddr_reg[1][1..0].q==3) --& rd_disp_en
;
SRdatad[7..0].d = rambuffer[3].q[7..0]&(rdaddr_reg[1][1..0].q==0) --& rd_disp_en
# rambuffer[2].q[7..0]&(rdaddr_reg[1][1..0].q==1) --& rd_disp_en
# rambuffer[1].q[7..0]&(rdaddr_reg[1][1..0].q==2) --& rd_disp_en
# rambuffer[0].q[7..0]&(rdaddr_reg[1][1..0].q==3) --& rd_disp_en
;
%
SRdataa[7..0].clk=rclock;
SRdatab[7..0].clk=rclock;
-- SRdatac[7..0].clk=rclock;
-- SRdatad[7..0].clk=rclock;
--------------------------------------------------------------------------------------------
------}}}}RAM-------------------------------------------------------------------------------
---------------------------------------------------------------{{{{计算部分
--------------------------------------------------------------------------
k[1][7..0] = h"b0";
k[2][7..0] = h"50";
k[3][7..0] = h"50";
k[4][7..0] = h"70";
----y0y1crcb分量regdata[1][7..0].d
reg_Y[0][7..0].d = SRdataa[7..0].q; ----第一次锁存
reg_Y[0][7..0].ena = pixcounterLo.q[0] == 0;
reg_Y[0][7..0].clk = fifo_rdclk ----fdotclk
;
reg_Y[1][7..0].d = SRdataa[7..0].q;
reg_Y[1][7..0].ena = pixcounterLo.q[0] == 1;
reg_Y[1][7..0].clk = fifo_rdclk ----fdotclk
;
reg_Cr[7..0].d = SRdatab[7..0].q;
reg_Cr[7..0].ena = pixcounterLo.q[0] == 0;
reg_Cr[7..0].clk = fifo_rdclk
;
reg_Cb[7..0].d = SRdatab[7..0].q;
reg_Cb[7..0].ena = pixcounterLo.q[0] == 1;
reg_Cb[7..0].clk = fifo_rdclk
;
reg_Y[1..0][15..8].d = reg_Y[1..0][7..0].q; ----第二次锁存
reg_Y[1..0][15..8].ena = pixcounterLo.q[0] == 0;
reg_Y[1..0][15..8].clk = fifo_rdclk;
reg_Cr[15..8].d = reg_Cr[7..0].q;
reg_Cr[15..8].ena = pixcounterLo.q[0] == 0;
reg_Cr[15..8].clk = fifo_rdclk;
reg_Cb[15..8].d = reg_Cb[7..0].q;
reg_Cb[15..8].ena = pixcounterLo.q[0] == 0;
reg_Cb[15..8].clk = fifo_rdclk;
----偶场
--red color
-- Red[0][7..0] = regdata_o[1][7..0].q + R_k1_v_mul[0].result[14..7];
-- Red[1][7..0] = regdata_o[1][23..16].q + R_k1_v_mul[0].result[14..7];
nd_reg_Y_add[0][7..0] = reg_Y[0][15..8].q;
nd_reg_Y_add[0][8] = b"0";
nd_reg_Y_add[1][7..0] = reg_Y[1][15..8].q;
nd_reg_Y_add[1][8] = b"0";
nd_reg_Y_sub[0][7..0] = reg_Y[0][15..8].q;
nd_reg_Y_sub[0][8] = b"1";
nd_reg_Y_sub[1][7..0] = reg_Y[1][15..8].q;
nd_reg_Y_sub[1][8] = b"1";
nd_k1_v_rst[7..0] = R_k1_v_mul[0].result[14..7]+1;
nd_k1_v_rst[8] = b"0";
if reg_Cr[15..8].q < h"80" then
cr_128_sub[7..0] = h"80" - reg_Cr[15..8].q ; --128 - cr
-- Red[0][7..0] = reg_Y[0][15..8].q - R_k1_v_mul[0].result[15..8];
-- Red[1][7..0] = reg_Y[1][15..8].q - R_k1_v_mul[0].result[15..8];
Red_delay[0][8..0].d = (nd_reg_Y_add[0][8..0] - nd_k1_v_rst[8..0])&!(nd_reg_Y_add[0][8..0] < nd_k1_v_rst[8..0]);
Red_delay[1][8..0].d = (nd_reg_Y_add[1][8..0] - nd_k1_v_rst[8..0])&!(nd_reg_Y_add[1][8..0] < nd_k1_v_rst[8..0]);
r_temp[0][8] = Red_delay[0][8].q;
r_temp[1][8] = Red_delay[1][8].q;
else
cr_128_sub[7..0] = reg_Cr[15..8].q - h"80"; --cr - 128
-- Red[0][7..0] = reg_Y[0][15..8].q + R_k1_v_mul[0].result[15..8];
-- Red[1][7..0] = reg_Y[1][15..8].q + R_k1_v_mul[0].result[15..8];
Red_delay[0][8..0].d = nd_reg_Y_add[0][8..0] + nd_k1_v_rst[8..0];
Red_delay[1][8..0].d = nd_reg_Y_add[1][8..0] + nd_k1_v_rst[8..0];
b_add_overflow[0] = Red_delay[0][8].q;
b_add_overflow[1] = Red_delay[1][8].q;
end if;
Red_delay[1..0][8..0].clk= rclock;
Red[0][8..0] = Red_delay[0][8..0].q;
Red[1][8..0] = Red_delay[1][8..0].q;
R_k1_v_mul[0].dataa[7..0] = k[1][7..0];
R_k1_v_mul[0].datab[7..0] = cr_128_sub[7..0];
R_k1_v_mul[0].clock = rclock;--accountclk;
--green color
--Green[0][7..0] = regdata_o[1][7..0].q - (G_k2_v_mul[0].result[15..8] + G_k3_u_mul[0].result[15..8]);
--Green[1][7..0] = regdata_o[1][23..16].q - (G_k2_v_mul[0].result[15..8] + G_k3_u_mul[0].result[15..8]);
nd_k2_v_rst[7..0] = G_k2_v_mul[0].result[15..8];
nd_k2_v_rst[8] = b"0";
nd_k3_u_rst[7..0] = G_k3_u_mul[0].result[15..8];
nd_k3_u_rst[8] = b"0";
reg_Y_delay[0][7..0].d = reg_Y[0][15..8].q;
reg_Y_delay[1][7..0].d = reg_Y[1][15..8].q;
reg_Y_delay[1..0][8].d = b"0";
reg_Y_delay[1..0][8..0].clk= rclock;
nd_k2_v_rst_delay[8..0].d= nd_k2_v_rst[8..0];
nd_k3_u_rst_delay[8..0].d= nd_k3_u_rst[8..0];
if reg_Cr[15..8].q < h"80" & reg_Cb[15..8].q < h"80" then
g_mul_com[0][8..0].d = nd_k2_v_rst[8..0] + nd_k3_u_rst[8..0];
g_mul_com[0][8..0].clk = rclock;
Green[0][8..0] = (reg_Y_delay[0][8..0].q + g_mul_com[0][8..0].q);
Green[1][8..0] = (reg_Y_delay[1][8..0].q + g_mul_com[0][8..0].q);
g_overflow[0][0] = Green[0][8];
g_overflow[1][0] = Green[1][8];
elsif reg_Cr[15..8].q < h"80" & reg_Cb[15..8].q > h"80" then
g_mul_com[1][8..0].d = nd_k3_u_rst_delay[8..0].q + nd_k2_v_rst_delay[8..0].q;
g_mul_com[1][8..0].clk = rclock;
Green[0][8..0] = (reg_Y_delay[0][8..0].q + nd_k2_v_rst_delay[8..0].q)- nd_k3_u_rst_delay[8..0].q
&!((reg_Y_delay[0][8..0].q + nd_k2_v_rst_delay[8..0].q)< nd_k3_u_rst_delay[8..0].q)
;
Green[1][8..0] = (reg_Y_delay[1][8..0].q + nd_k2_v_rst_delay[8..0].q)- nd_k3_u_rst_delay[8..0].q
&!((reg_Y_delay[1][8..0].q + nd_k2_v_rst_delay[8..0].q)< nd_k3_u_rst_delay[8..0].q)
;
g_overflow[0][0] = Green[0][8];
g_overflow[1][0] = Green[1][8];
elsif reg_Cr[15..8].q > h"80" & reg_Cb[15..8].q < h"80" then
g_mul_com[2][8..0].d = nd_k3_u_rst[8..0] - nd_k2_v_rst[8..0];
g_mul_com[2][8..0].clk = rclock;
Green[0][8..0] = (reg_Y_delay[0][8..0].q + nd_k3_u_rst_delay[8..0].q)- nd_k2_v_rst_delay[8..0].q
&!((reg_Y_delay[0][8..0].q + nd_k3_u_rst_delay[8..0].q)< nd_k2_v_rst_delay[8..0].q)
;
Green[1][8..0] = (reg_Y_delay[1][8..0].q + nd_k3_u_rst_delay[8..0].q)- nd_k2_v_rst_delay[8..0].q
&!((reg_Y_delay[1][8..0].q + nd_k3_u_rst_delay[8..0].q)< nd_k2_v_rst_delay[8..0].q)
;
g_overflow[0][0] = Green[0][8];
g_overflow[1][0] = Green[1][8];
else
g_mul_com[3][8..0].d = nd_k2_v_rst[8..0] + nd_k3_u_rst[8..0];
g_mul_com[3][8..0].clk = rclock;
Green[0][8..0] = reg_Y_delay[0][8..0].q - g_mul_com[3][8..0].q
&!(reg_Y_delay[0][8..0].q < g_mul_com[3][8..0].q)
;
Green[1][8..0] = reg_Y_delay[1][8..0].q - g_mul_com[3][8..0].q
&!(reg_Y_delay[1][8..0].q < g_mul_com[3][8..0].q)
;
end if;
G_k2_v_mul[0].dataa[7..0] = k[2][7..0];
G_k2_v_mul[0].datab[7..0] = cr_128_sub[7..0];
G_k2_v_mul[0].clock = rclock;
G_k3_u_mul[0].dataa[7..0] = k[3][7..0];
G_k3_u_mul[0].datab[7..0] = cb_128_sub[7..0];
G_k3_u_mul[0].clock = rclock;
--blue color
-- Blue[0][7..0] = regdata_o[1][7..0].q + B_k4_u_mul[0].result[15..8];
-- Blue[1][7..0] = regdata_o[1][23..16].q + B_k4_u_mul[0].result[15..8];
nd_k4_u_rst[7..0] = B_k4_u_mul[0].result[14..7]+1;
nd_k4_u_rst[8] = b"0";
if reg_Cb[15..8].q < h"80" then
cb_128_sub[7..0] = h"80" - reg_Cb[15..8].q ; ---128 - cb
-- Blue[0][7..0] = reg_Y[0][15..8].q - B_k4_u_mul[0].result[15..8];
-- Blue[1][7..0] = reg_Y[1][15..8].q - B_k4_u_mul[0].result[15..8];
Blue_delay[0][8..0].d = (nd_reg_Y_add[0][8..0] - nd_k4_u_rst[8..0])
&!(nd_reg_Y_add[0][8..0] < nd_k4_u_rst[8..0]);
Blue_delay[1][8..0].d = (nd_reg_Y_add[1][8..0] - nd_k4_u_rst[8..0])
&!(nd_reg_Y_add[1][8..0] < nd_k4_u_rst[8..0]);
b_temp[0][8] = Blue_delay[0][8].q;
b_temp[1][8] = Blue_delay[1][8].q;
else
cb_128_sub[7..0] = reg_Cb[15..8].q - h"80"; ---cb - 128
-- Blue[0][7..0] = reg_Y[0][15..8].q + B_k4_u_mul[0].result[15..8];
-- Blue[1][7..0] = reg_Y[1][15..8].q + B_k4_u_mul[0].result[15..8];
Blue_delay[0][8..0].d = nd_reg_Y_add[0][8..0] + nd_k4_u_rst[8..0];
Blue_delay[1][8..0].d = nd_reg_Y_add[1][8..0] + nd_k4_u_rst[8..0];
b_temp[2][8] = Blue_delay[0][8].q;
b_temp[3][8] = Blue_delay[1][8].q;
end if;
Blue_delay[1..0][8..0].clk= rclock;
Blue[0][8..0] = Blue_delay[0][8..0].q;
Blue[1][8..0] = Blue_delay[1][8..0].q;
B_k4_u_mul[0].dataa[7..0] = k[4][7..0];
B_k4_u_mul[0].datab[7..0] = cb_128_sub[7..0];
B_k4_u_mul[0].clock = rclock;
------}}}}}计算结束--------------------------------
---------------------------------------------------
----输出到640
----像素输出
pix_out_R[0][7..0] = (red[0][7..0] & !b_add_overflow[0] # vcc & b_add_overflow[0]) & av_ram_test_h[1].q----
# reg_Y[0][15..8].q
& av_ram_test_h[0].q--
;
pix_out_R[0][15..8] = (red[1][7..0] & !b_add_overflow[1] # vcc & b_add_overflow[1]) & av_ram_test_h[1].q----
# reg_Y[1][15..8].q
& av_ram_test_h[0].q--
;
pix_out_G[0][7..0] = ((green[0][7..0] & !g_overflow[0][0] ) # (vcc & g_overflow[0][0]))& av_ram_test_h[2].q----
# reg_Cb[15..8].q
& av_ram_test_h[0].q--reg_Y[0][15..8]
;
pix_out_G[0][15..8] = ((green[1][7..0]& !g_overflow[1][0] ) # (vcc & g_overflow[1][0]))& av_ram_test_h[2].q----
# reg_Cb[15..8].q
& av_ram_test_h[0].q--reg_Y[1][15..8]
;
pix_out_B[0][7..0] = (blue[0][7..0] & !b_temp[2][8] # vcc & b_temp[2][8]) & av_ram_test_h[3].q----
# reg_Cr[15..8].q
& av_ram_test_h[0].q--reg_Y[0][15..8]
;
pix_out_B[0][15..8] = (blue[1][7..0] & !b_temp[3][8] # vcc & b_temp[3][8]) & av_ram_test_h[3].q----
# reg_Cr[15..8].q
& av_ram_test_h[0].q--reg_Y[1][15..8]
;
---------------------------------------------------------------------------------------------------
---------******************************二次插值结束************************************}}}}}}}-----
---------------------------------------------------------------------------------------------------
----power on reset
--复位计数器
-- = reset_count.q[7..0]
reset_count.clock = ad_clk/1;
reset_count.clk_en =!reset_ctl_reg[3].q;
--计数器脉冲
reset_ctl_reg[0].d =(reset_count.q[7..0]==h"80");
reset_ctl_reg[0].clk = ad_clk/1;
--计数器脉冲
reset_ctl_reg[1].d =(reset_count.q[7..0]==h"ff");
reset_ctl_reg[1].clk = ad_clk/1;
--复位输出
reset_ctl_reg[2].d = reset_ctl_reg[2].q;
reset_ctl_reg[2].clrn =!reset_ctl_reg[0].q;
reset_ctl_reg[2].prn =!reset_ctl_reg[1].q;
reset_ctl_reg[2].clk = ad_clk/1;
--复位计数器时钟允许控制
reset_ctl_reg[3].d = vcc;
reset_ctl_reg[3].clrn =!reset_ctl_reg[0].q;
--reset_ctl_reg[3].prn =!reset_ctl_reg[1].q;
reset_ctl_reg[3].clk = reset_ctl_reg[2].q;
resetn = reset_ctl_reg[2].q; --输出负向复位脉冲
----delay register; pulse
----图形场同步脉冲
fvsync_delay_reg[0].d = fvsync;
fvsync_delay_reg[1].d = fvsync_delay_reg[0].q;
fvsync_delay_reg[2].d = fvsync_delay_reg[1].q;
fvsync_delay_reg[3].d = fvsync_delay_reg[2].q;
fvsync_delay_reg[4].d = fvsync_delay_reg[3].q;
fvsync_delay_reg[4..0].clk = fldclk;
fvsync_pulse =!fvsync_delay_reg[0].q & fvsync_delay_reg[4].q;
----图形行同步脉冲
fhsync_delay_reg[0].d = fhsync;
fhsync_delay_reg[1].d = fhsync_delay_reg[0].q;
fhsync_delay_reg[1..0].clk = fldclk;
fhsync_pulse =!fhsync_delay_reg[0].q & fhsync_delay_reg[1].q;
----图形行消隐信号脉冲
fblank_delay_reg[0].d = fblank;
fblank_delay_reg[1].d = fblank_delay_reg[0].q;
fblank_delay_reg[2].d = fblank_delay_reg[1].q;
fblank_delay_reg[2..0].clk = fldclk;
fblank_sta_pulse[0] =!fblank_delay_reg[0].q & fblank_delay_reg[1].q;
fblank_sta_pulse[1] =!fblank_delay_reg[0].q & fblank_delay_reg[2].q;
----*****************************--
----******* REG INITIAL *********--
----*****************************--
----***************************************
----************* I2C BUS ***********
----WRITE GM5020 AND SAA7114 REGISTERS 50c0h
SDA_TRI.IN = gnd;
SDA_TRI.OE =(id==0)&!SDAREG[0].Q &!(!fRD_DELAY_reg[1].q & SDA_ADDR);
IICSDA = SDA_TRI.OUT;
----I2C CLOCK BIT0 OF REGISTER 50c8h
SCL_TRI.IN = gnd; --SCLREG[0].Q;
SCL_TRI.OE =(id==0)&!SCLREG[0].Q;
IICSCL = SCL_TRI.OUT;
%
----sii178 iic control
dvi_scl = ctlreg3[0].q & resetn_in_delay; --6018 bit0
dvi_sda_tri.oe =!ctlreg4[0].q --6020 bit0
#!resetn_in_delay;
dvi_sda_tri.in = GND;
dvi_sda = dvi_sda_tri.out;
%
----************************************************--
%
EXT ADDR (14)13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBMD ADDR (38)37 36 35 34 33 32 31 30 29 28 27 X X X
extla 10 9 8 7 6 5 4 3 2 1 0
"h" | | | |
rgb640 (1) 0 0 0 0 0 0 0 0 x x x --4000..403f
%
--***** ADDRESS SELECTION *****--
-- || || || |
RGB640_ADDR = (EXTLA[10..3]==B"00000000" ); --4000..403f
640_index_l_addr = (EXTLA[10..0]==B"00000000100"); --4020
640_index_h_addr = (EXTLA[10..0]==B"00000000101"); --4028
640_index_data_addr = (EXTLA[10..0]==B"00000000110"); --4030
%
WIN_X_O_H_ADDR = (EXTLA[10..0]==B"01000000000"); --5000 --改为2..0bit A路ENA 6..4bit B.ena
WIN_X_O_L_ADDR = (EXTLA[10..0]==B"01000000001"); --5008 --bit2 禁止RAM写允许
WIN_Y_O_H_ADDR = (EXTLA[10..0]==B"01000000010"); --5010 --改为2..0bit C路ENA 6..4bit C.ena
WIN_Y_O_L_ADDR = (EXTLA[10..0]==B"01000000011"); --5018 --640装载时钟反向
SIGNAL_SWITCH_ADDR = (EXTLA[10..0]==B"01000000100"); --5020 -- BIT 0 改为直通控制
WIN_RESOLUTION_ADDR = (EXTLA[10..0]==B"01000000101"); --5028 -- BIT 0
A_DISPLAY_ADDR = (EXTLA[10..0]==B"01000000110"); --5030
a_freeze_ADDR = (EXTLA[10..0]==B"01000000111"); --5038 --fifo禁止写允许
W_G_WIDTH_ADDR = (EXTLA[10..0]==B"01000001000"); --5040 --第2组 ENA
W_G_DEPTH_ADDR = (EXTLA[10..0]==B"01000001001"); --5048 --bit1二选一亮度和色度的选择
%
SDA_ADDR = (EXTLA[10..0]==B"01000001010"); --5050
SCL_ADDR = (EXTLA[10..0]==B"01000001011"); --5058
PRI_ADDR = (EXTLA[10..0]==B"01000001100"); --5060
%
OC_OUT_CTL_ADDR = (EXTLA[10..0]==B"01000010000"); --5080
TTL_IN_CTL_ADDR = (EXTLA[10..0]==B"01000010010"); --5090
SW_IN_CTL_ADDR = (EXTLA[10..0]==B"01000010100"); --50a0
SELF_TEST_ADDR = (EXTLA[10..0]==B"01000010110"); --50b0
%
%
tv_ctl_ADDR = (EXTLA[10..0]==B"01000010111"); --50b8
TV_H_START_h_ADDR = (EXTLA[10..0]==B"01000011000"); --50c0
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