📄 fpga_yuv2rgb.tdf
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LPM_WIDTH = 1,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
%
---读地址计数器--与像素计数器用的时钟不一样
rd_addr_count_Lo : lpm_counter WITH (
LPM_WIDTH = 11,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
rd_addr_count_Hi : lpm_counter WITH (
LPM_WIDTH = 11,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
---像素计数器
pixcounterLo : lpm_counter WITH (
LPM_WIDTH = 11,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
--场计数器
pixcounterHi : lpm_counter WITH (
LPM_WIDTH = 10,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
fvsync_count : lpm_counter WITH (
LPM_WIDTH = 9,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
-------------------------------------------------------乘法器
dx_x_mul : lpm_mult WITH ( --比例系数乘行计数计算浮点坐标
LPM_WIDTHA = 8, --比例系数
LPM_WIDTHB = 8, --乘行计数器
LPM_WIDTHP = 16,
LPM_WIDTHS = 16,
INPUT_B_IS_CONSTANT = "NO",
LPM_REPRESENTATION = "UNSIGNED",
USE_EAB = "OFF",
LPM_PIPELINE = 4
);
R_k1_v_mul[1..0] : lpm_mult WITH ( --RED = Y+k1*(v-128)
LPM_WIDTHA = 8, --k1
LPM_WIDTHB = 8, --v-128
LPM_WIDTHP = 16,
LPM_WIDTHS = 16,
INPUT_B_IS_CONSTANT = "NO",
LPM_REPRESENTATION = "UNSIGNED",
USE_EAB = "OFF",
LPM_PIPELINE = 4
);
G_k2_v_mul[1..0] : lpm_mult WITH ( --GREEN = Y+k2*(v-128) - k3*(u-128)
LPM_WIDTHA = 8, --k2
LPM_WIDTHB = 8, --v-128
LPM_WIDTHP = 16,
LPM_WIDTHS = 16,
INPUT_B_IS_CONSTANT = "NO",
LPM_REPRESENTATION = "UNSIGNED",
USE_EAB = "OFF",
LPM_PIPELINE = 4
);
G_k3_u_mul[1..0] : lpm_mult WITH ( --GREEN = Y+k2*(v-128) - k3*(u-128)
LPM_WIDTHA = 8, --k3
LPM_WIDTHB = 8, --u-128
LPM_WIDTHP = 16,
LPM_WIDTHS = 16,
INPUT_B_IS_CONSTANT = "NO",
LPM_REPRESENTATION = "UNSIGNED",
USE_EAB = "OFF",
LPM_PIPELINE = 4
);
B_k4_u_mul[1..0] : lpm_mult WITH ( --BLUE = Y+ k4*(u-128)
LPM_WIDTHA = 8, --k3
LPM_WIDTHB = 8, --u-128
LPM_WIDTHP = 16,
LPM_WIDTHS = 16,
INPUT_B_IS_CONSTANT = "NO",
LPM_REPRESENTATION = "UNSIGNED",
USE_EAB = "OFF",
LPM_PIPELINE = 4
);
u_128_sub : lpm_add_sub WITH (
LPM_WIDTH = 8,
LPM_DIRECTION = "SUB",
LPM_TYPE = "LPM_ADD_SUB",
LPM_HINT = "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=YES",
LPM_PIPELINE = 1
);
y0_k1mulv_add : lpm_add_sub WITH (
LPM_WIDTH = 8,
LPM_DIRECTION = "ADD",
LPM_TYPE = "LPM_ADD_SUB",
LPM_HINT = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
);
y1_k1mulv_add : lpm_add_sub WITH (
LPM_WIDTH = 8,
LPM_DIRECTION = "ADD",
LPM_TYPE = "LPM_ADD_SUB",
LPM_HINT = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
);
y0_k1mulv_sub : lpm_add_sub WITH (
LPM_WIDTH = 8,
LPM_DIRECTION = "SUB",
LPM_TYPE = "LPM_ADD_SUB",
LPM_HINT = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
);
y1_k1mulv_sub : lpm_add_sub WITH (
LPM_WIDTH = 8,
LPM_DIRECTION = "SUB",
LPM_TYPE = "LPM_ADD_SUB",
LPM_HINT = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
);
----------------------------------------------------mult end
--------------------------------------------------------------------------
-----$$$$$$$$$$$$$$$$$$$$$$二次插值定义结束$$$$$$$$$$$$$$$$$$$$---------
--------------------------------------------------------------------------
----#############################################################----
----#############################################################----
BEGIN
----#############################################################----
----#############################################################----
----FPGA ID NUMBER SELECT;u65 id==0; u66 id==1;
ID = ID1_ID0;
----test
test[0] = (id==0)& reset_count.q[7]
#(id==1)& fhsync_pulse
;
19_19 = test_node[4]
;
--u65-94pin
test_node[0]= gnd--ram_wen[0]--R_k1_v_mul.result[15]----ram_wen[0]--pixcounterHi.q[1] --SRdataa[1].q--regdata[1][1].q--tv_display--FVSYNC
;
--u65-96pin
test_node[1]= gnd--tv_display--R_k1_v_mul.result[14]----SRdataa[0].q--regdata[1][0].q--rambuffer[0].q[1]
;
--u65-206pin
test_node[2]= gnd--ramwrclock--R_k1_v_mul.result[13]----v_zoom_out--SRdatab[1].q--regdata[1][17].q--rambuffer[0].q[0]
;
--u65-207pin
test_node[3]= gnd--rd_addr_count_Lo.q[0]--R_k1_v_mul.result[12]----SRdatab[0].q--regdata[1][16].q---rambuffer[2].q[1]
;
--u65-19pin
test_node[4]= gnd--tv_display--rambuffer[2].q[0]----ram_read_addr[0][7]
;
testreg.d = !testreg.q;
testreg.clk = FAUXOUT;
-------------------------------------------------------------------------------------------------
-----{{{{{{********************************为二次插值修改*************************************---
-------------------------------------------------------------------------------------------------
rclock = fdotclk;--form 640
ramwrclock = fdotclk;--pixcounterLo.q[0]; --fifo_rdclk 1/2;
accountclk = pixcounterLo.q[1]; --fifo_rdclk 1/4;
---------------------------------------------------------{{{FIFO
-------------**********************************************-----------------
------------- 计数器 -----------------
-------------**********************************************-----------------
----数据选择计数器
%
--select_data_count.q[0] =
select_data_count.clock = fifo_rdclk----fdotclk
;
select_data_count.sclr = fvsync_pulse; --& HSYNC;
select_data_count.cnt_en = tv_display;
%
----fvsync_count场同步计数器
fvsync_count.clock = fvsync;
----产生RAM读地址计数器
--高
rd_addr_count_Hi.clock = fhsync_pulse;--rclock;rd_addr_count_Lo.q[8..0]==h"1ff";---
--
rd_addr_count_Hi.aclr = fvsync_pulse;
rd_addr_count_Hi.cnt_en = TV_V_READY;
--低
rd_addr_count_Lo.clock = fdotclk;
rd_addr_count_Lo.sclr = fhsync_pulse; --& HSYNC;
rd_addr_count_Lo.cnt_en = tv_display;
----产生RAM写地址计数器
---高
--计数器时钟
pixcounterHi.clock = fhsync_pulse-----(FAUXOUT)pixcounterLo.q[8..0]==h"1ff"--
;
--计数器异步清零
pixcounterHi.aclr = fvsync_pulse --& fhsync
;
pixcounterHi.cnt_en= TV_V_READY;
---低
pixcounterLo.clock = fifo_rdclk ----fdotclk
;
--计数器异步清0
pixcounterLo.aclr = fhsync_pulse
;
pixcounterLo.cnt_en = tv_display;
------7114计数器
--7114场同步计数器
--7114_vsync_count.q[1..0]
7114_vsync_count.aclr = vsync_pulse_o;
7114_vsync_count.clock=!(VSYNC & HSYNC);
--7114 pix_count像素计数器
7114_pix_count.clock = fdclk;
7114_pix_count.aclr = hsync_pulse;
--7114 行同步计数器
7114_hsync_count.clock = HSYNC;
7114_hsync_count.aclr = vsync_pulse_o;
----产生7114行同步脉冲
HSYNC =!GMH;
VSYNC =!GMV;
hsync_reg[0].d = GMH;
hsync_reg[1].d = hsync_reg[0].q;
hsync_reg[2].d = hsync_reg[1].q;
hsync_reg[3].d = hsync_reg[2].q;
hsync_reg[3..0].clk = fdclk;
hsync_pulse = hsync_reg[0].q & !hsync_reg[3].q;
----产生7114场同步脉冲
vsync_reg[0].d = GMV;
vsync_reg[1].d = vsync_reg[0].q;
vsync_reg[2].d = vsync_reg[1].q;
vsync_reg[3].d = vsync_reg[2].q;
vsync_reg[3..0].clk = fdclk;
vsync_pulse = !vsync_reg[0].q & vsync_reg[3].q;
vsync_pulse_o = vsync_pulse & HSYNC;
----FIFO的bit[1..0]测试信号
fifo_test_sign[0]=!7114_vsync_count.q[1];
fifo_test_sign[1]=!7114_hsync_count.q[0];
--------------------------------------------------------------------------------
--产生每一场的FIFO写允许
fifo_v_wen_o = 7114_hsync_count.q[10..0] > 23 & 7114_hsync_count.q[10..0] < 320;
fifo_v_wen_j = 7114_hsync_count.q[10..0] > 336 & 7114_hsync_count.q[10..0] < 623;
--产生每一行的FIFO写允许
fifo_h_wen = 7114_pix_count.q[10..0] > 80 & 7114_pix_count.q[10..0] <= 1104;--592;
--FIFO写允许
fifo_wen_o = 7114_vsync_count.q[1] & fifo_h_wen & fifo_v_wen_o %& !a_freeze[0].q% %& fifo_wr_ctl_reg.q%;--ffwen0 偶数场与行同步与reg5038
fifo_wen_j =!7114_vsync_count.q[1] & fifo_h_wen & fifo_v_wen_j %& !a_freeze[0].q% %& fifo_wr_ctl_reg.q%;--ffwen1 奇数场与行同步与reg5038
--FIFO写重置
fifo_wrst = vsync_pulse_o;
--FIFO读时钟
fifo_rdclk = fdotclk --& v_zoom_out!=1
;
--FIFO读允许
fifo_ren = tv_display --放大时地址相同禁止读FIFO
;
--FIFO读重置
fifo_rrst = fvsync_pulse;
--FIFO输出数据
fifo_do_o[7] = GBAGRN[5];
fifo_do_o[6] = GBAGRN[6];
fifo_do_o[5] = GBAGRN[7];
fifo_do_o[4] = GBARED[3];
fifo_do_o[3] = GBARED[4];
fifo_do_o[2] = GBARED[5];
fifo_do_o[1] = GBARED[6];
fifo_do_o[0] = GBARED[7];--gnd;
fifo_do_j[7] = GBAGRN[4];
fifo_do_j[6] = GBAGRN[3];
fifo_do_j[5] = GBAGRN[2];
fifo_do_j[4] = GBABLU[7];
fifo_do_j[3] = GBABLU[6];
fifo_do_j[2] = GBABLU[5];
fifo_do_j[1] = GBABLU[4];
fifo_do_j[0] = GBABLU[3];--gnd
----------------------------------------------------------}}}FIFO
----
ram_disp_0data[7..0] = fifo_do_o[7..0] --& tv_display- & !HSYNC%rdaddress[0][7..0]%
# h"ff" & count_cmp & av_ram_test_h[4].q
;
ram_disp_1data[7..0] = fifo_do_j[7..0] --& tv_display; --& !HSYNC;
# h"ff" & ((pixcounterLo.q[8..1]-1) == (pixcounterHi.q[7..0]+fvsync_count.q[7..0]))%count_cmp% & av_ram_test_h[4].q
;
----测试两计数器相等产生测试线
count_cmp = (pixcounterLo.q[8..1] == (pixcounterHi.q[7..0]+fvsync_count.q[7..0]))
;
--fifo输入数据二选一Y crcb 偶数场
regdata[0][7..0].d = ram_disp_0data[7..0]; ---y0 y1
regdata[0][7..0].ena = pixcounterLo.q[0] == 0;
regdata[0][7..0].clk = fifo_rdclk
;
regdata[0][15..8].d = ram_disp_0data[7..0]; ---cr cb
regdata[0][15..8].ena = pixcounterLo.q[0] == 1;
regdata[0][15..8].clk = fifo_rdclk
;
--fifo输入数据二选一Y crcb 奇数场
regdata[1][7..0].d = ram_disp_1data[7..0]; ----y
regdata[1][7..0].ena = pixcounterLo.q[0] == 0;
regdata[1][7..0].clk = fifo_rdclk
;
regdata[1][15..8].d = ram_disp_1data[7..0]; ----cr cb
regdata[1][15..8].ena = pixcounterLo.q[0] == 1;
regdata[1][15..8].clk = fifo_rdclk
;
------{{{{RAM*************************************************************************
--------------------------------------------------------------------------------------
---------*****************************************************************************
---RAM输出数据 在某一时刻同时取两行(两块RAM)数据
------{{{{RAM----
---RAM输出数据 在某一时刻同时取两行(两块RAM)数据
--节点RAM读地址
ram_readaddr[8..0] = rd_addr_count_Lo.q[8..0];
ram_readaddr[10..9] = pixcounterHi.q[1..0]+1;
--节点RAM写地址
ram_writeaddr[7..0] = pixcounterLo.q[8..1];
ram_writeaddr[9..8] = pixcounterHi.q[1..0]+1;
--ram 写时钟
rambuffer[3..0].wrclock = ramwrclock --1/2 fdotclk
;
--ram 写允许
rambuffer[3..0].wren = ram_wen[3..0] %& !win_x_o_l_value[2]%;
ram_wen[0] =(pixcounterLo.q[0]==0)%&(pixcounterLo.q[9..0] < H"1ff")%;-- ;--y0 y1
ram_wen[1] =(pixcounterLo.q[0]==1)%&(pixcounterLo.q[9..0] < H"1ff")%;-- ;--cr cb
ram_wen[2] =(pixcounterLo.q[0]==0)%&(pixcounterLo.q[9..0] < H"1ff")%;-- ;--y0 y1
ram_wen[3] =(pixcounterLo.q[0]==1)%&(pixcounterLo.q[9..0] < H"1ff")%;-- ;--cr cb
--RAM写地址 //由行计数器产生
rambuffer[3..0].wraddress[8..0] = ram_write_addr[3..0][8..0];
ram_write_addr[3..0][7..0] = ram_writeaddr[7..0];
ram_write_addr[3..0][8] = ram_writeaddr[8];
%
--RAM输入数据
rambuffer[1..0].data[7..0] = regdata[0][7..0].q; --偶数场经过二选一数据
rambuffer[3..2].data[7..0] = regdata[0][7..0].q; --奇数场经过二选一数据
%
--RAM输入数据
rambuffer[0].data[7..0] = regdata[0][7..0].q; ----偶数场经过二选一数据y0 y1
rambuffer[1].data[7..0] = regdata[0][15..8].q; ----cr cb
rambuffer[2].data[7..0] = regdata[1][7..0].q; ----奇数场经过二选一数据
rambuffer[3].data[7..0] = regdata[1][15..8].q; ----cr cb
--ram 读时钟
rambuffer[3..0].rdclock = rclock;
--RAM读地址
rambuffer[3..0].rdaddress[8..0] = ram_read_addr[3..0][8..0];
rdaddr_reg[0][0].d = ram_readaddr[0];
rdaddr_reg[0][1].d = ram_readaddr[9];
rdaddr_reg[1][1..0].d = rdaddr_reg[0][1..0].q;
rdaddr_reg[1..0][1..0].clk = rclock;
ram_read_addr[0][8..0] = ram_readaddr[8..0];--rdaddr[8..0]+ rdaddr_bit[0][8..0]+ rdaddr_bit[1][8..0];
ram_read_addr[1][8..0] = ram_readaddr[8..0];--rdaddr[8..0] + rdaddr_bit[1][8..0];
ram_read_addr[2][8..0] = ram_readaddr[8..0];--rdaddr[8..0]+ rdaddr_bit[0][8..0] ;
ram_read_addr[3][8..0] = ram_readaddr[8..0];--rdaddr[8..0] ;
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