📄 fpga_yuv2rgb.tdf
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TV_H_END[10..0] :node;
--TV_H_POSITION[10..0] :node;
TV_H_READY_HOLD[2..1] :dffe;
TV_H_READY :node;
TV_V_START[10..0] :node;
TV_V_END[10..0] :node;
--TV_V_POSITION[9..0] :node;
TV_V_READY :node;
tv_h_offset_value[10..0] :node;
----TV OUTPUT ENABLE *****--
tv_pix_en :node;
TV_DISPLAY :node;
tv_display_reg[1..0] :dffe;
--TV_COVER_AV :node;
----********电视像素数据*********
tv_pix_blu_a_reg[4..0] :dffe;
tv_pix_grn_a_reg[5..0] :dffe;
tv_pix_red_a_reg[4..0] :dffe;
tv_pix_blu_b_reg[4..0] :dffe;
tv_pix_grn_b_reg[5..0] :dffe;
tv_pix_red_b_reg[4..0] :dffe;
tv_pix_a[23..0] :node;
tv_pix_b[23..0] :node;
5020_tpix_a[23..0] :node;
5020_tpix_b[23..0] :node;
--tv_pix_reg[1..0][15..0] :dffe;
-- TV_DATA_EVEN[23..0] :dffe;
-- TV_DATA_LATCH :TFF;
-- GMDEN_JUDGEMENT :node;
-- GMDEN_DELAY[1..0] :dffe;
----**************************************************
----************** STORE ad data *************
----**************************************************
----SELECT THE MAX DATA IN INPUT DATA
ad_d_clrn_reg[1..0] :dffe;
ad_d_reg[1..0][7..0] :dffe;
ad_d_data[4..0][7..0] :node;
----FREQUENCY GENERATOR
----
ad_clk/1 :node;
ad_clk/2 :node;
ad_clk/4 :node;
wram_addr_clk :node;
--*****MODE SELECT*****
ku/ts_sta_pulse[1..0] :node;
ku/ms0_sta_pulse[1..0] :node;
-- ku/ms1_sta_pulse[1..0] :node;
ka/ts_sta_pulse[1..0] :node;
ka/ms0_sta_pulse[1..0] :node;
-- ka/ms1_sta_pulse[1..0] :node;
ku/ts_sta_addr[11..0] :node;
ku/ms0_sta_addr[11..0] :node;
ku/ms1_sta_addr[11..0] :node;
ka/ts_sta_addr[11..0] :node;
ka/ms0_sta_addr[11..0] :node;
ka/ms1_sta_addr[11..0] :node;
ku/ts_end_addr[11..0] :node;
ku/ms0_end_addr[11..0] :node;
ku/ms1_end_addr[11..0] :node;
ka/ts_end_addr[11..0] :node;
ka/ms0_end_addr[11..0] :node;
ka/ms1_end_addr[11..0] :node;
TSDELAY[2..0] :dffe; --TS DELAY SIGNAL REGISTER
MSDELAY[2..0] :dffe; --MS DELAY SIGNAL REGISTER
ka/ku :node;
--*****av_ram EAB RAM*****
---- 512+512+328+328+328+328 = 1824;1824/4=456
av_ram[0] --6 x 16 x 256 EAB RAM
: lpm_ram_dp WITH (
LPM_WIDTH = 24,
LPM_WIDTHAD = 10,
RDEN_USED = "FALSE",
INTENDED_DEVICE_FAMILY = "FLEX10KE",
LPM_TYPE = "LPM_RAM_DP",
LPM_INDATA = "REGISTERED",
LPM_WRADDRESS_CONTROL = "REGISTERED",
LPM_RDADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "av",
USE_EAB = "ON"
);
av_ram_wren[5..0] :node;
av_ram_wrclock :node;
av_ram_wraddr[9..0] :node;
av_ram_wrdata[23..0] :node;
av_ram_wrdata_reg[17..0] :dffe;
----*****************************************--
----**************** 显示控制 ****************--
----RAM_DATA_VALUE[5..0] :dffe;
av_ram_out[0][23..0] :node;
av_ram_out_a[2..0][5..0] :node;
av_ram_out_b[2..0][5..0] :node;
av_ram_out_c[2..0][5..0] :node;
av_ram_out_d[2..0][5..0] :node;
av_ram_out_a_reg[1..0][5..0]:dffe;
av_ram_out_b_reg[1..0][5..0]:dffe;
av_ram_out_c_reg[1..0][5..0]:dffe;
av_ram_out_d_reg[1..0][5..0]:dffe;
----***************************************--
----*********** DATA OUTPUT ***************--
av_ram_pix_en_reg[2..0] :dffe;
av_ram_pix_en[2..0] :node;
av_data[15..0] :node;
av_pix_en :node;
soe_ctl :node;
wid_ctl[7..0] :node;
FACBLU_TRI[7..0] :TRI;
FACGRN_TRI[7..0] :TRI;
FACRED_TRI[7..0] :TRI;
FBDBLU_TRI[7..0] :TRI;
FBDGRN_TRI[7..0] :TRI;
FBDRED_TRI[7..0] :tri;
--*********** wid OUTPUT ***************--
wid0_ffrckd_tri :tri;
wid1_c51d2_tri :tri;
wid2_c51d1_tri :tri;
wid3_soectl3_tri :tri; --soectl3
wid4_soectl1_tri :tri;
wid5_soectl0_tri :tri;
wid6_ffwe_tri :tri; --FIFO WRITE ENABLE
wid7_FFWRST_tri :tri; --FIFO WRITE ADDRESS RESET
207_FFRRST_tri :tri; --FIFO READ ADDRESS RESET
206_FFRE_tri :tri; --FIFO READ ENABLE
--*********** VRAM INTERRUPT ************--
96_SOE2_TRI :TRI;
SOE_TV_SET[1..0] :dffe;
SOE_TV :node;
SOE_AV_SET[1..0] :dffe;
SOE_AV :node;
SOE_DELAY :dffe;
----***************************************
----************ OTHERS ****************
----***** A_VIDEO OUTPUT ENABLE ***********
AV_DISPLAY :node;
av_display_reg[6..0] :dffe;
AV_COVER_TV :node;
ADCLK_TRI :TRI;
ADOE_TRI :TRI;
--AV_DATA[7..0] :node;
----***** SELF TEST *****--
ARBLK,ADDL,ARCF,ARAD :dffe;
arad_value :node;
arcf_value :node;
addl_value :node;
arblk_value :node;
ARBLK_CLRN :dffe;
ARCF_TS,ARCF_MS :dffe;
SELF_CLRN[1..0] :dffe;
----***** OC GATE *****--
OC_TTL_TRI[7..0] :TRI;
----***** OTHER SIGNALS *****
94_c51d0_TRI,
PBLANK_D3_TRI :TRI;
----***** CONNECT TO RGB640 *****--
dacrstn_tri :tri;
DACWR_TRI :TRI;
DACRD_TRI :TRI;
REFCLK_TRI :TRI;
RGB640_ADDR :node;
--------------------------------------------------------------------------
----$$$$$$$$$$$$$$$$$$$$$$二次插值定义$$$$$$$$$$$$$$$$$$$$------------
--------------------------------------------------------------------------
test_sub[7..0] :node;
ramwrclock : node; --RAM写时钟
rclock : node;
--SYNC
HSYNC : node; --输入行同步控制
VSYNC : node; --输入场同步控制
-- HREF : node; --消隐信号
--ram
ram_disp_1data[7..0] : node;
ram_disp_0data[7..0] : node; --外部输入的pix 8位数据
OHSYNC : node;
OVSYNC : node;
-- OHREF : node;
outclock : node;
output1data[7..0] : node;
output2data[7..0] : node;
ram_readaddr[10..0] : node;
ram_writeaddr[10..0] : node;
pix_out[31..0] : node;
pix_out_R[3..0][31..0] : node;
pix_out_G[3..0][31..0] : node;
pix_out_B[3..0][31..0] : node;
vsync_pulse : node; --场同步脉冲
hsync_pulse : node; --行同步脉冲
count_cmp : node; --测试两计数器相等
nx_n[3..0] : node;
ny_n[3..0] : node;
rd_disp_en : node;
fifo_rdclk : node;
fifo_rrst : node;
fifo_ren : node;
fifo_wrst : node;
fifo_wen_j : node;
fifo_wen_o : node;
fifo_do_j[7..0] : node; --偶数场fifo输出数据
fifo_do_o[7..0] : node; --偶数场fifo输出数据
vsync_pulse_o : node; --偶数场脉冲
v_zoom_out : node; --y方向缩小 -两次计算行的读地址比较相等
v_zoom_in : node; --y方向放大 -两次计算行的读地址之差为2
fifo_h_wen : node;
fifo_v_wen_o : node;
fifo_v_wen_j : node;
fifo_test_sign[1..0] : node;
hsync_reg[3..0] :dffe; --用于产生行脉冲
vsync_reg[3..0] :dffe; --用于产生场脉冲
clk_reg[1..0] :dffe; --用于二分频时钟输出给640
regdata[2..0][31..0] :dffe;
regdata_j[2..0][31..0] :dffe;
regdata_R[2..0][31..0] :dffe; --直通
regdata_G[2..0][31..0] :dffe;
regdata_B[2..0][31..0] :dffe;
hsync_new_reg[1..0] :dffe;
ram_data_reg[3..0][7..0] :dffe;
ram_read_addr_reg[0][8..0] :dffe;
rdaddr[8..0] :node;
ram_read_addr[3..0][8..0] :node;
ram_write_addr[3..0][8..0] :node;
addr_inc[10..0] :node;
ram_wren[3..0] :node;
rdaddr_reg[1..0][1..0] :dffe;
rdaddr_bit[1..0][8..0] :node;
data_out_reg[3..0][7..0] :dffe;
fifo_rd_sign_reg :dffe;
fifo_wr_ctl_reg :dffe;
testreg :dffe;
reg_Y[1..0][15..0] :dffe; ---YUV寄存器
reg_CrCb[1..0][15..0] :dffe;
reg_Cr[15..0] :dffe;
reg_Cb[15..0] :dffe;
reg_U_delay[3..0][15..0] :dffe;
reg_V_delay[3..0][15..0] :dffe;
g_mul_com[3..0][8..0] :dffe;
reg_Y_delay[1..0][8..0] :dffe;
Red_delay[1..0][8..0] :dffe;
Blue_delay[1..0][8..0] :dffe;
nd_k2_v_rst_delay[8..0] :dffe;
nd_k3_u_rst_delay[8..0] :dffe;
k[4..1][7..0] :node; ---系数
Red[1..0][15..0] :node;
Green[1..0][15..0] :node;
Blue[1..0][15..0] :node;
cr_128_sub[8..0] :node;
cb_128_sub[8..0] :node;
nd_reg_Y_add[1..0][8..0] :node;
nd_reg_Y_sub[1..0][8..0] :node;
nd_k1_v_rst[8..0] :node;
nd_k4_u_rst[8..0] :node;
nd_k2_v_rst[8..0] :node;
nd_k3_u_rst[8..0] :node;
r_temp[3..0][8..0] :node;
b_temp[3..0][8..0] :node;
g_overflow[1..0][3..0] :node;
b_add_overflow[1..0] :node;
g_overflow_sub[1..0] :node;
----------原定义
-- wrclock :dff; --ram写时钟
regclk :dffe; --二分频时钟
----------------------
cxa[3..0] :dffe; --(比例系数小数部分)
cxb[3..0] :dffe; --1-(比例系数小数部分)
cxa_reg[9..0][3..0] :dffe;
cxb_reg[9..0][3..0] :dffe;
cya[3..0] :dffe;
cyb[3..0] :dffe;
cya_reg[9..0][3..0] :dffe;
cyb_reg[9..0][3..0] :dffe;
tempa[3..0] :dffe; --存储小数的中间暂存
tempb[3..0] :dffe;
vtempa[3..0] :dffe;
vtempb[3..0] :dffe;
rdaddress[3..0][10..0] :dffe; --ram读地址
SRdataa[7..0] :dffe; --原数据0
SRdatab[7..0] :dffe; --原数据1
SRdatac[7..0] :dffe; --原数据2
SRdatad[7..0] :dffe; --原数据3
ny[12..0] :dffe; --变化后坐标
nx[12..0] :dffe;
ram_rdaddr[5..0][10..0] :node;
ram_wraddr[5..0][10..0] :node;
ram_wen[3..0] :node;
accountclk :node;
x_scale_dataa[3..0] :dffe; --主机传递scale startad endad 数据
y_scale_dataa[3..0] :dffe; --主机传递 Y scale 缩放系数
xa[10..0] :dffe; --整数
xb[10..0] :dffe; --整数+1
ya[10..0] :dffe;
yb[10..0] :dffe;
--------原定义结束
-------------------------------------------------------RAM
rambuffer[5..0]
: lpm_ram_dp WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 9,
RDEN_USED = "FALSE",
INTENDED_DEVICE_FAMILY = "FLEX10KE",
LPM_TYPE = "LPM_RAM_DP",
LPM_INDATA = "REGISTERED",
LPM_WRADDRESS_CONTROL = "REGISTERED",
LPM_RDADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
-- LPM_FILE = "av",
USE_EAB = "ON"
);
------------------------------------------------------计数器
7114_hsync_count : lpm_counter WITH (
LPM_WIDTH = 11,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
--7114场同步计数器
7114_vsync_count : lpm_counter WITH (
LPM_WIDTH = 2,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
7114_pix_count : lpm_counter WITH (
LPM_WIDTH = 11,
LPM_TYPE = "LPM_COUNTER",
LPM_DIRECTION = "UP"
);
%
select_data_count : lpm_counter WITH (
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