📄 fpga_yuv2rgb.tdf
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INCLUDE "lpm_and.inc";
INCLUDE "lpm_add_sub.inc";
INCLUDE "lpm_counter.inc";
INCLUDE "lpm_mult.inc";
INCLUDE "altdpram.inc";
INCLUDE "lpm_ff.inc";
INCLUDE "lpm_ram_dp.inc";
SUBDESIGN cgl400e_u65
(
----***** FIFO AND GM5020 *****
GMDEN,GMH,GMV :input; --gmh gmv 7114 hsync vsync
fdclk :input; --7114 clock 27mhz
--wid7_FFWRST --FIFO WRITE ADDRESS RESET
--wid6_ffwe --FIFO WRITE ENABLE
-- --FIFO WRITE CLOCK FIFO写时钟是7114来的27M时钟
207_FFRRST :OUTPUT;--FIFO READ ADDRESS RESET
206_FFRE :OUTPUT;--FIFO READ ENABLE
--wid0_ffrckd --fifo read clock
fdotclk :INPUT; --FIFO READ CLOCK 640的点频时钟,最高频率
----TV SIGNAL INPUT
GBABLU[7..3] :input;
GBAGRN[7..2] :input;
GBARED[7..3] :input;
----SWITCH INPUT
k0[3..0] :INPUT; --u65 INPUT k[a b c d]; u66 INPUT k[e f g h]
----OC GATE AND TTL GATE
OC_TTL[7..0] :BIDIR; --U65 OUTPUT OC[7..0]; U66 INPUT TTL[7..0]
----LBUS CONTROL SIGNALS
LBMD[47..40] :BIDIR; --lbus data
EXTLA[10..0] :INPUT; --lbus address
FWR_,FRD_ :INPUT; --WRITE AND READ STROBE FROM LBUS
GMCLK :INPUT; --GLINT WORK CLOCK
FVSYNC :INPUT; ----FROM GLINT OUTPUT;
FHSYNC :INPUT; ----FROM GLINT OUTPUT;
FBLANK :INPUT; --FROM GLINT OUTPUT;--INPUT; --FROM GLINT 改为vcc
DACRST_ :bidir; --FROM GLINT,RESET SIGNAL
----I2C
IICSCL :BIDIR;
IICSDA :BIDIR;
----A_VIDEO SIGNALS
TS,MS,KA_KU :INPUT; --SYNCHRONIZE SIGNAL
GATE :INPUT; --WAVE GATE SIGNAL
ADCLK :BIDIR; --AD CLOCK
ADOE_ :BIDIR; --A/D OUTPU--T ENABLE
AD_D[8..1] :INPUT; --7114 data y0 u0 y1 v0 y2 u2 y3 v2
----*****RAM*****
FLDCLK : INPUT; --glint load clock;RAM OUTPUT CLOCK 640 Load clock
----READ_DATA : INPUT; --RAM READ START SIGNAL
----***** DATA OUTPUT *****
FACBLU[7..0] : BIDIR; --FPGA OUTPUT DATA,OUTPUT CLOCK SHOULD BE FLDCLK
FACGRN[7..0] : BIDIR;
FACRED[7..0] : BIDIR;
FBDBLU[7..0] : BIDIR;
FBDGRN[7..0] : BIDIR;
FBDRED[7..0] : BIDIR;
----wid control
wid0_ffrckd : bidir;
wid1_c51d2 : bidir;
wid2_c51d1 : bidir;
wid3_soectl3 : bidir; --soectl3
wid4_soectl1 : bidir;
wid5_soectl0 : bidir;
wid6_ffwe : bidir; --FIFO WRITE ENABLE
wid7_FFWRST : bidir; --FIFO WRITE ADDRESS RESET
----***** VRAM INTERRUPT *****
96_SOE2 :BIDIR;
----***** TO RGB640 *****--
DACWR_ :BIDIR; --地址译码后将总线的读写信号送到RGB640的读写pin上
DACRD_ :BIDIR; --地址为4000～4038
REFCLK :BIDIR; -- TO RGB640,CONNECT WITH GMCLK DIRECTLY
VCLK :INPUT; --STANDBY CLOCK, NO USE IN THIS VERSION
----**** FPGA ID SELECTION *****--
ID1_ID0 :INPUT; --ID SELECT INPUT
----***** C51 SIGNALS *****--
94_c51d0,
PBLANK_D3 :BIDIR;
----***** OTHER SIGNALS *****
FPGACLK :bidir; --40.96MHZ
FAUXOUT :input; --STANDBY CLOCK, NO USE IN THIS VERSION
fulsclk :bidir; --rem从u65到u66传送 b 路像素在窗口中的扫描线位置
----*****TEST OUTPUT FOR SIMULATION*****
test[0] :output;
19_19 :output;
)
----################################################################----
VARIABLE
----################################################################----
----power on reset counter
reset_count
: lpm_counter WITH (
LPM_WIDTH = 8,
LPM_DIRECTION = "UP"
);
reset_ctl_reg[3..0] :dffe;
resetn :node;
----
ID :node; --ID SELECT device
----test node
test_node[4..0] :node;
----delay register
fvsync_delay_reg[4..0] :dffe;
fhsync_delay_reg[1..0] :dffe;
fblank_delay_reg[2..0] :dffe;
----node;hsync vsync blank
fvsync_pulse :node;
fhsync_pulse :node;
fblank_sta_pulse[1..0] :node;
----********** I2C & BUS READ AND WRITE **********--
----************************************************--
LDA_TRI[7..0] :TRI;
frd_delay_reg[1..0] :dffe;
fwr_delay_reg[1..0] :dffe;
----I2C DATA LINE; REG ADDRESS 5050 BIT 0
SDA_ADDR :node;
SDAREG[0] :dffe;
SDAREG_value[7..0] :node;
SDA_TRI :TRI;
----I2C CLOCK LINE; REG ADDRESS 5058 BIT 0
SCL_ADDR :node;
SCLREG[0] :DFFE;
SCLREG_value[7..0] :DFFE;
SCL_TRI :TRI;
----************************************************--
----**** INTERFACE REGISTERS DEFINITION *****--
----************************************************--
----rgb640 interface register
640_index_l_reg[7..0] :DFFE;
640_index_l_addr :node;
640_index_h_reg[7..0] :DFFE;
640_index_h_addr :node;
640_index_data_addr :node;
640_index_012c_addr :node;
640_index_012c_data[7..0] :node;
%
----x coordinates of window top left corner; REG ADDRESS 5000-H,5008-L
WIN_X_O_H_ADDR :node;
WIN_X_O_H[7..0] :DFFE;
WIN_X_O_h_value[7..0] :node;
WIN_X_O_L_ADDR :node;
WIN_X_O_L[2..0] :DFFE;
WIN_X_O_L_value[7..0] :node;
WIN_X_O[10..0] :node;
----Y coordiantes of window top left corner; reg address 5010-H, 5018-L
WIN_Y_O_H_ADDR :node;
WIN_Y_O_H[7..0] :DFFE;
WIN_Y_O_h_value[7..0] :node;
WIN_Y_O_L_ADDR :node;
WIN_Y_O_L[2..0] :DFFE;
WIN_Y_O_L_value[7..0] :node;
WIN1_Y_O[10..0] :node;
----SIGNAL SWITCH ; reg address 5020 BIT0: IF # = 0 ,SHUT DOWN SIGNAL SOURCE
SIGNAL_SWITCH_ADDR :node;
SIGNAL_SWITCH[0] :DFFE;
SIGNAL_SWITCH_value[7..0] :node;
----REG ADDRESS 5028 BIT 0: IF # = 0 THEN 512X480 ELSE 412X360
WIN_RESOLUTION_ADDR :node;
WIN_RESOLUTION[0] :DFFE;
WIN_RESOLUTION_value[7..0] :node;
----SIX SCREEN OF A_DISPLAY ENABLE; REG ADDRESS 5030
A_DISPLAY_ADDR :node;
A_DISPLAY[5..0] :DFFE;
A_DISPLAY_value[7..0] :node;
----FREEZE DISPLAY; REG ADDRESS 5038 BIT0: IF # = 0 , NORMAL OPERATION, ELSE FREEZE DISPLAY
a_freeze_value[7..0] :node;
a_freeze_ADDR :node;
a_freeze[0] :DFFE;
----WAVE GATE WIDTH; REG ADDRESS 5040
W_G_WIDTH_ADDR :node;
W_G_WIDTH[7..0] :DFFE;
W_G_WIDTH_value[7..0] :node;
----WAVE GATE DEPTH; REG ADDRESS 5048
W_G_DEPTH_ADDR :node;
W_G_DEPTH[1..0] :DFFE;
W_G_DEPTH_value[7..0] :node;
%
----AV_WINDOW & TV_WINDOW PRI; REG ADDRESS 5060 BIT0
PRI_ADDR :node;
PRI[0] :DFFE;
PRI_value[7..0] :node;
%
----OC GATE OUTPUT REGISTER; REG ADDRESS 5080
OC_OUT_CTL_ADDR :node;
OC_OUT_CTL[7..0] :DFFE;
OC_OUT_CTL_value[7..0] :node;
----TTL INPUT REGISTER; REG ADDRESS 5090 (READ ONLY)
TTL_IN_CTL_ADDR :node;
TTL_IN_CTL_value[7..0] :node;
----SWITCH INPUT REGISTER; REG ADDRESS 50A0 (READ ONLY)
SW_IN_CTL_ADDR :node;
SW_IN_CTL_value[7..0] :node;
----SELF TEST REGISTER; REF ADDRESS 50B0 (READ ONLY)
SELF_TEST_ADDR :node;
SELF_TEST_value[7..0] :node;
%
----TV control REGISTER; REF ADDRESS 50b8
tv_ctl[4..0] :dffe;
tv_ctl_value[7..0] :node;
tv_ctl_addr :node;
TV_H_START_H[7..0] :dffe;
TV_H_START_H_ADDR :node;
tv_h_START_L[2..0] :dffe;
TV_H_START_L_ADDR :node;
tv_h_start_l_value[7..0] :node;
----TV WINDOW H POSITION END REGISTER; REF ADDRESS 50D0-H,50D8-L
TV_H_END_H[7..0] :dffe;
TV_H_END_H_ADDR :node;
TV_H_END_L[2..0] :dffe;
TV_H_END_L_ADDR :node;
tv_h_end_l_value[7..0] :node;
----TV WINDOW V POSITION START REGISTER; REF ADDRESS 50E0-H,50E8-L
TV_V_START_H[7..0] :dffe;
TV_V_START_H_ADDR :node;
TV_V_START_L[2..0] :DFFE;
TV_V_START_L_ADDR :node;
tv_v_start_l_value[7..0] :node;
--TV WINDOW V POSITION END REGISTER; REF ADDRESS 50F0-H,50F8-L
TV_V_END_H[7..0] :DFFE;
TV_V_END_H_ADDR :node;
TV_V_END_L[2..0] :DFFE;
TV_V_END_L_ADDR :node;
tv_v_end_l_value[7..0] :node;
----av test register
av_ram_test_l[7..0] :dffe; --5100
av_ram_test_h[7..0] :dffe; --5108
av_ram_test_d[7..0] :dffe; --5110
av_ram_test_l_addr :node;
av_ram_test_h_addr :node;
av_ram_test_d_addr :node;
test_ts :node;
test_ms :node;
test_ka/ku :node;
test_wram_addr[11..0] :node;
--**************************************************--
--*************** A_DIDEO WINDOWS ****************--
--**************************************************--
WIN_WIDTH[10..0] :node;
win_ms_width[10..0] :node;
WIN_HEIGHT[10..0] :node;
A_H_READY_HOLD[2..0] :dffe;
--H_READY_REG :dffe;
--V_READY_REG :dffe;
--WIN_Y_O[9..0] :dffe;
--WIN1_Y_O[10..0] :NODE;
WIN2_Y_O[10..0] :NODE;
WIN3_Y_O[10..0] :node;
WIN4_Y_O[10..0] :node;
WIN5_Y_O[10..0] :node;
WIN6_Y_O[10..0] :node;
----av x display count
A_H_COUNTER : lpm_counter WITH (
LPM_WIDTH = 11,
LPM_DIRECTION = "UP"
);
----av y display count
A_V_COUNTER : lpm_counter WITH (
LPM_WIDTH = 11,
LPM_DIRECTION = "UP"
);
A_H_POSITION[10..0] :node;
A_H_READY :node;
a_h_ms_ready :node;
A_V_POSITION[10..0] :node;
A_V_READY :node;
WIN_ID[6..1] :dffe;
----av windows h/v offset
a_h_offset_reg[7..0] :dffe;
a_h_offset_value[8..0] :node;
--a_v_offset_reg[7..0] :dffe;
--a_v_offset_value[10..0] :node;
----**************************************************
----************** TV SIGNALS ******************
----**************************************************
----5020 input
--gmh_tri :tri;
--gmv_tri :tri;
--gmden_tri :tri;
--fpgaclk_tri :tri;
----tv DISPLAY WINDOWS
%
TV_H_COUNTER : lpm_counter WITH (
LPM_WIDTH = 11,
LPM_DIRECTION = "UP"
);
%
%
TV_V_COUNTER : lpm_counter WITH (
LPM_WIDTH = 10,
LPM_DIRECTION = "UP"
);
%
TV_H_START[10..0] :node;
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