wrsbcarm9.h.bak

s3c2410的烧片程序,用ads编译,可以通过串口或者jtag口烧写

#define rROMCON4      0x60
#define rROMCON5      0x60        /*ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5*/

/****************************************************************************
 * -> DRAMCON0 : RAM Bank0 control register  (EDO)
 */
#define EDO_Mode0          1             /*(EDO)0=Normal, 1=EDO DRAM*/
#define CasPrechargeTime0  1             /*(Tcp)0=1cycle,1=2cycle*/
#define CasStrobeTime0     1             /*(Tcs)0=1cycle ~ 3=4cycle*/
#define DRAMCON0Reserved   1             /* Must be set to 1*/
#define RAS2CASDelay0      0             /*(Trc)0=1cycle,1=2cycle*/
#define RASPrechargeTime0  1             /*(Trp)0=1cycle ~ 3=4clcyle*/
#define DRAMBasePtr0       (0x100<<10)   /*=0x1000000 */
#define DRAMBasePtr0_S     0x00          /* now RAM moved to zero */


#define DRAMEndPtr0        (((LOCAL_MEM_SIZE >> 16) + 0x100) << 20)  /*=0x00800000 - 8 MB */
#define DRAMEndPtr0_S      ((LOCAL_MEM_SIZE >> 16) << 20)  /*=0x00800000 - 8 MB */

#define NoColumnAddr0      2             /*0=8bit,1=9bit,2=10bit,3=11bits*/

#define Tcs0           (CasStrobeTime0<<1)
#define Tcp0           (CasPrechargeTime0<<3)
#define dumy0          (DRAMCON0Reserved<<4)        /*dummy cycle*/
#define Trc0           (RAS2CASDelay0<<7)
#define Trp0           (RASPrechargeTime0<<8)
#define CAN0           (NoColumnAddr0<<30)

#define rDRAMCON0      (CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)
#define rDRAMCON0_S    (CAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)

/****************************************************************************
 * -> DRAMCONx : unused RAM Banks
 */
#define rDRAMCON1         0x00
#define rDRAMCON2         0x00
#define rDRAMCON3         0x00

/****************************************************************************
 * -> DRAMCON0 : RAM Bank0 control register (for SDRAM)
 */
#define SRAS2CASDelay0          1                    /*(Trc)0=1cycle,1=2cycle*/
#define SRASPrechargeTime0      3                    /*(Trp)0=1cycle ~ 3=4cycle*/
#define SCasPrechargeTime0      0                    /*(Tcp)0=1cycle,1=2cycle*/
#define SCasStrobeTime0         0                    /*(Tcs)0=1cycle ~ 3=4cycle*/
#define SNoColumnAddr0          0                    /*0=8bit,1=9bit,2=10bit,3=11bits*/
#define SCAN0                   (SNoColumnAddr0<<30)
#define STrc0                   (SRAS2CASDelay0<<7)
#define STrp0                   (SRASPrechargeTime0<<8)
#define STcp0                   (SCasPrechargeTime0<<3)
#define STcs0                   (SCasStrobeTime0<<1)

#define rSDRAMCON0              (SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0+STcp0+STcs0)
#define rSDRAMCON0_S            (SCAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+STrp0+STrc0+STcp0+STcs0)

/****************************************************************************
 * -> DRAMCONx : unused SYNC DRAM Banks
 */
#define rSDRAMCON1        0x00
#define rSDRAMCON2        0x00
#define rSDRAMCON3        0x00

/**************************************************************************
 * -> REFEXTCON : External I/O & Memory Refresh cycle Control Register 
 */

#define RefCycle          16         /*Unit [us], 1k refresh 16ms*/

/*RefCycle EQU 8 ;Unit [us], 1k refresh 16ms*/

#define CASSetupTime         0         /*0=1cycle, 1=2cycle*/
#define CASHoldTime          0         /*0=1cycle, 1=2cycle, 2=3cycle,
                                         3=4cycle, 4=5cycle,*/
#if (((2<<11)+1-(RefCycle*fMCLK)) < 0x3FF)
#define RefCycleValue     (((2<<11)+1-(RefCycle*fMCLK))<<21)
#else
#define RefCycleValue     (0x3FF<<21)
#endif

#define Tcsr              (CASSetupTime<<20) /* 1cycle */
#define Tcs               (CASHoldTime<<17)
#define ExtIOBase         0x183fd            /* Refresh enable, VSF=1*/

#define rREFEXTCON        (RefCycleValue+Tcsr+Tcs+ExtIOBase)

/******************************************************************
 *SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms
 */

#define SRefCycle          8         /*Unit [us], 4k refresh 64ms*/
#define ROWcycleTime       3         /*0=1cycle, 1=2cycle, 2=3cycle,
                                       3=4cycle, 4=5cycle,*/
#define SRefCycleValue     ((2048+1-(SRefCycle*fMCLK))<<21)
#define STrc               (ROWcycleTime<<17)
#define rSREFEXTCON        (SRefCycleValue+STrc+ExtIOBase)

#endif /*#if 0*/

#define INT_LVL_EXTINT0       0    /* External Interrupt0 */
#define INT_LVL_EXTINT1       1    /* External Interrupt1 */
#define INT_LVL_EXTINT2       2    /* External Interrupt2 */
#define INT_LVL_EXTINT3       3    /* External Interrupt3 */
#define INT_LVL_EXTINT4_7       4    /* External Interrupt4/5/6/7 */
#define INT_LVL_EXTINT8_23       5    /* External Interrupt8-23*/
#define INT_LVL_BATT_FLT		7
#define INT_LVL_TICK          8  
#define INT_LVL_WDT           9
#define INT_LVL_TIMER0        10    /* Timer 0 Interrupt */
#define INT_LVL_TIMER1        11    /* Timer 1 Interrupt  */
#define INT_LVL_TIMER2        12
#define INT_LVL_TIMER3        13
#define INT_LVL_TIMER4         14
#define INT_LVL_UART2        15    /* UART 0 Transmit Interrupt */
#define INT_LVL_LCD				16
#define INT_LVL_DMA0         17    
#define INT_LVL_DMA1         18    
#define INT_LVL_DMA2         19    
#define INT_LVL_DMA3         20  
#define INT_LVL_SDI			 21
#define INT_LVL_SPI0		 22
#define INT_LVL_UART1        23
#define INT_LVL_USBD		 25
#define INT_LVL_USBH		 26
#define INT_LVL_IIC			 27
#define INT_LVL_UART0        28
#define INT_LVL_SPI1		 29
#define INT_LVL_RTC          30
#define INT_LVL_ADC            31


#define SUBINT_LVL_RXD0		0
#define SUBINT_LVL_TXD0		1
#define SUBINT_LVL_ERR0		2
#define SUBINT_LVL_RXD1		3
#define SUBINT_LVL_TXD1		4
#define SUBINT_LVL_ERR1		5
#define SUBINT_LVL_RXD2		6
#define SUBINT_LVL_TXD2		7
#define SUBINT_LVL_ERR2		8
#define SUBINT_LVL_TC		9
#define SUBINT_LVL_ADC		10



/* interrupt vectors */
#define INT_VEC_EXTINT0       IVEC_TO_INUM(INT_LVL_EXTINT0)    /* External Interrupt0 */
#define INT_VEC_EXTINT1       IVEC_TO_INUM(INT_LVL_EXTINT1)    /* External Interrupt1 */
#define INT_VEC_EXTINT2       IVEC_TO_INUM(INT_LVL_EXTINT2)    /* External Interrupt2 */
#define INT_VEC_EXTINT3       IVEC_TO_INUM(INT_LVL_EXTINT3)    /* External Interrupt3 */
#define INT_VEC_EXTINT4_7     IVEC_TO_INUM(INT_LVL_EXTINT4_7)    /* External Interrupt4/5/6/7 */
#define INT_VEC_EXTINT8_23    IVEC_TO_INUM(INT_LVL_EXTINT8_23)    /* External Interrupt8-23*/
#define INT_VEC_BATT_FLT	  IVEC_TO_INUM(INT_LVL_BATT_FLT)
#define INT_VEC_TICK          IVEC_TO_INUM(INT_LVL_TICK)  
#define INT_VEC_WDT           IVEC_TO_INUM(INT_LVL_WDT)
#define INT_VEC_TIMER0        IVEC_TO_INUM(INT_LVL_TIMER0)    
#define INT_VEC_TIMER1        IVEC_TO_INUM(INT_LVL_TIMER1)    
#define INT_VEC_TIMER2        IVEC_TO_INUM(INT_LVL_TIMER2)
#define INT_VEC_TIMER3        IVEC_TO_INUM(INT_LVL_TIMER3)
#define INT_VEC_TIMER4        IVEC_TO_INUM(INT_LVL_TIMER4)
#define INT_VEC_UART2         IVEC_TO_INUM(INT_LVL_UART2)    
#define INT_VEC_LCD			  IVEC_TO_INUM(INT_LVL_LCD)
#define INT_VEC_DMA0          IVEC_TO_INUM(INT_LVL_DMA0)    
#define INT_VEC_DMA1          IVEC_TO_INUM(INT_LVL_DMA1)    
#define INT_VEC_DMA2          IVEC_TO_INUM(INT_LVL_DMA2)    
#define INT_VEC_DMA3          IVEC_TO_INUM(INT_LVL_DMA3)  
#define INT_VEC_SDI			  IVEC_TO_INUM(INT_LVL_SDI)
#define INT_VEC_SPI0		  IVEC_TO_INUM(INT_LVL_SPI0)
#define INT_VEC_UART1         IVEC_TO_INUM(INT_LVL_UART1)
#define INT_VEC_USBD		  IVEC_TO_INUM(INT_LVL_USBD)
#define INT_VEC_USBH		  IVEC_TO_INUM(INT_LVL_USBH)
#define INT_VEC_IIC			  IVEC_TO_INUM(INT_LVL_IIC)
#define INT_VEC_UART0         IVEC_TO_INUM(INT_LVL_UART0)
#define INT_VEC_SPI1		  IVEC_TO_INUM(INT_LVL_SPI1)
#define INT_VEC_RTC           IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_ADC           IVEC_TO_INUM(INT_LVL_ADC)





/**********************************************************************************************************
 * Cache Definitions
 *
 */

#define SBCARM9_CACHE_0K   	 	(0<<1)
#define SBCARM9_CACHE_4K        (1<<1)
#define SBCARM9_CACHE_8K        (3<<1)
#define SBCARM9_WRITE_BUFF      (1<<3)
#define SBCARM9_CACHE_MODE      0x0E

#define SBCARM9_CACHE_SIZE		SBCARM9_CACHE_8K

#define NON_CACHE_REGION    	0		/*TODO*/
#define SBCARM9_TAGRAM_BEG 0x10002000 
#define SBCARM9_TAGRAM_END 0x10004800  

#define SBCARM9_TIMER_SYS_TC_DISABLE    (TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM9_TIMER_SYS_TC_ENABLE     (TC_ENABLE  | TC_PERIODIC | TC_DIV16)
#define SBCARM9_TIMER_AUX_TC_DISABLE    (TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SBCARM9_TIMER_AUX_TC_ENABLE     (TC_ENABLE  | TC_PERIODIC | TC_DIV16)

#define SYS_TIMER_CLK               (SBCARM9_CPU_SPEED)    /* Frequency of counter/timer */
#define AUX_TIMER_CLK               (SBCARM9_CPU_SPEED)    /* Frequency of counter/timer */

#define SBCARM9_RELOAD_TICKS            3        

#define SYS_TIMER_CLEAR(x)          (SBCARM9_TIMER_T1CLEAR(x))    
#define SYS_TIMER_CTRL(x)           (SBCARM9_TIMER_T1CTRL(x))
#define SYS_TIMER_LOAD(x)           (SBCARM9_TIMER_T1LOAD(x))
#define SYS_TIMER_VALUE(x)          (SBCARM9_TIMER_T1VALUE(x))
#define SBCARM9_TIMER_VALUE_MASK        0xFFFF
#define AUX_TIMER_CLEAR(x)          (SBCARM9_TIMER_T2CLEAR(x))   
#define AUX_TIMER_CTRL(x)           (SBCARM9_TIMER_T2CTRL(x))
#define AUX_TIMER_LOAD(x)           (SBCARM9_TIMER_T2LOAD(x))
#define AUX_TIMER_VALUE(x)          (SBCARM9_TIMER_T2VALUE(x))

#define SYS_TIMER_INT_LVL           (INT_LVL_TIMER0)
#define AUX_TIMER_INT_LVL           (INT_LVL_TIMER1)

/******************************************************************************************
 */

#define SYS_CLK_RATE_MIN      10  
#define SYS_CLK_RATE_MAX      10000
#define AUX_CLK_RATE_MIN      2 		
#define AUX_CLK_RATE_MAX      10000
#define SBCARM9_RESET_RAM_BASE    0x1000000  

/*
 */

#define ETHERNET_MAC_ADRS { 0x00, 0xA0, 0x88, 0x88, 0x88, 0x00 }

#ifdef __cplusplus
}
#endif

#endif    /* INCsbcarm9h */