wrsbcarm9.h.bak

s3c2410的烧片程序,用ads编译,可以通过串口或者jtag口烧写

/* sbcarm9.h - WindRiver SBC ARM9 header file */

/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"


#ifndef    INCsbcarm9h
#define    INCsbcarm9h

#ifdef __cplusplus
extern "C" {
#endif

#include "s3c2410x.h"

#define S3C_EXC_BASE         0x30000100	/* : added */

#define TARGET_SBCARM9


#define SBCARM9_FLASH_BASE 0x01000000


#define LOCAL_MEM_LOCAL_ADRS  0x30000000    /* fixed */
#define LOCAL_MEM_BUS_ADRS    0x00000000    /* fixed */


#define BUS                   BUS_TYPE_NONE

#define SBCARM9_CPU_SPEED         192000000    /* CPU clocked at 50 MHz. The timer */




#define N_SBCARM9_UART_CHANNELS     2        /* number of SBCARM9 UART chans */
#define N_SIO_CHANNELS          N_SBCARM9_UART_CHANNELS
#define N_UART_CHANNELS         N_SBCARM9_UART_CHANNELS
#define UART_REG_ADDR_INTERVAL  1        /* registers 4 bytes apart */


/* LED Registers (write) */
#define  SBCARM9_LEDREG             0x3fd4000

/* USER DIP switch (read) */
#define  SBCARM9_USERREG            0x3fd4000
#define READ_USERDIP()              (*((volatile char *)SBCARM9_USERREG) & 0xff)

#define DRAM_BASE           0x30000000   /* Final start address of DRAM */
#define DRAM_LIMIT          0x2000000
#define RESET_DRAM_START    0x30000000   
#define RESET_ROM_START     0x0         

/******************watch dog******************/
#define rWTCON_INIT_VALUE			(0x00000000)

/****************************************************************************
 *
 * Format of the Program Status Register 
 */

#define FBit         0x40
#define IBit         0x80
#define LOCKOUT      0xC0    
#define LOCK_MSK     0xC0     
#define MODE_MASK    0x1F     
#define UDF_MODE     0x1B    
#define ABT_MODE     0x17    
#define SUP_MODE     0x13     
#define IRQ_MODE     0x12    
#define FIQ_MODE     0x11     
#define USR_MODE     0x10     

/*************************************************************************
 * SYSTEM CLOCK 
 */

#define MHz            1000000
#define fMCLK_MHz      192000000     /* 50MHz, KS32C50100*/
#define fMCLK          192           /* fMCLK_MHz/MHz */


/*************************************************************************
 * SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
 */

#define SYSCONFIG_VAL_SDRAM     0x00000000    /* System Configuration Value, SDRAM */


#define S3C2410X_SYSCFG   0x07ffffa0
#define tCDIV           (0<<0)
#define tWE             (0<<16)
#define tMUX            (0<<17)
#define tAC             (0<<18)
#define tTEST           (0<<31)

#define rCLKCON			0x7ff00	    /*All unit block CLK enable*/
#define rCLKSLOW		0x00000084
#define rCLKDIVN		0x00000003

#define tCOS0           (1<<0)
#define tACS0           (1<<3)
#define tCOH0           (1<<6)
#define tACC0           (1<<9)
#define tCOS1           (1<<16)
#define tACS1           (1<<19)
#define tCOH1           (1<<22)
#define tACC1           (1<<25)

#define rEXTACON0    (tCOS0+tACS0+tCOH0+tACC0+tCOS1+tACS1+tCOH1+tACC1)

#define tCOS2           (7<<0)
#define tACS2           (7<<3)
#define tCOH2           (7<<6)
#define tACC2           (7<<9)
#define tCOS3           (7<<16)
#define tACS3           (7<<19)
#define tCOH3           (7<<22)
#define tACC3           (7<<25)

#define rEXTACON1    (tCOS2+tACS2+tCOH2+tACC2+tCOS3+tACS3+tCOH3+tACC3)

#define DSR0  (3<<0)     
#define DSR1  (1<<2)     
#define DSR2  (1<<4)    
#define DSR3  (0<<6)    
#define DSR4  (0<<8)    
#define DSR5  (0<<10)    
#define DSD0  (3<<12)   
#define DSD1  (0<<14)   
#define DSD2  (0<<16)    
#define DSD3  (0<<18)   
#define DSX0  (0<<20)    
#define DSX1  (1<<22)   
#define DSX2  (1<<24)  
#define DSX3  (1<<26)   

#define rEXTDBWTH  		0x11110110

#define B0_Tacs         0x0     /*0clk*/
#define B0_Tcos         0x0     /*0clk*/
#define B0_Tacc         0x7     /*10clk*/
#define B0_Tcoh         0x0     /*0clk*/
#define B0_Tah          0x0     /*0clk*/
#define B0_Tacp         0x0     /*0clk*/
#define B0_PMC          0x0     /*normal(1data)*/
#define rROMCON0 ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
#define rROMCON1		rROMCON0
#define B2_Tacs         0x0     /*4clk*/
#define B2_Tcos         0x0     /*4clk*/
#define B2_Tacc         0x7     /*14clk*/
#define B2_Tcoh         0x0     /*4clk*/
#define B2_Tah          0x0     /*4clk*/
#define B2_Tacp         0x0     /*6clk*/
#define B2_PMC          0x0     /*normal(1data)*/
#define rROMCON2 ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
/*CPLD2 Exernal (Net)*/
#define rROMCON3		rROMCON2
/*CPLD3 USER FREE*/
#define rROMCON4		rROMCON2
/*CPLD4 Internal*/
#define rROMCON5		rROMCON2

/*SDRAM1 Bank 6 parameter*/
/*BDRAMTYPE="DRAM"       ;MT=01(FP DRAM) or 10(EDO DRAM)*/ 
#define B6_MT           0x3     /*SDRAM*/
#define B6_Trcd         0x2     /*2clk*/
#define B6_SCAN         0x1     /*8bit*/
#define rSDRAMCON0 ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
/*SDRAM2 Bank 7 parameter*/
#define rSDRAMCON1		rSDRAMCON0

#define REFEN           0x1     /*Refresh enable*/
#define TREFMD          0x0     /*CBR(CAS before RAS)/Auto refresh*/
#define Trp             0x0     
#define Trc             0x3    
#define Tchr            0x0     
#define REFCNT          1113    
#define rSREFEXTCON ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)

#define rBANKSIZE		((0<<7)+(1<<5)+(1<<4)+(2))	
#define rMRSRB6			0x30	
#define rMRSRB7			0x30	

#define MM_DIV   		88      /*Fout = Fin * 2*/
#define MP_DIV   		1
#define MS_DIV   		1

#define rMPLLCON  ((MM_DIV<<12)+(MP_DIV<<4)+MS_DIV)	/*Fin=10MHz,Fout=40MHz*/

#define UM_DIV   		0x78      /*Fout = Fin * 2*/
#define UP_DIV   		2
#define US_DIV   		3

#define rUPLLCON  ((UM_DIV<<12)+(UP_DIV<<4)+US_DIV)	/*Fin=10MHz,Fout=40MHz*/

#define rLOCKTIME		0xffffff
/* : added++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */

#if 0 /* : deleted */
/***********************************************************
 *
 * -> ROMCON0 : ROM Bank0 Control register 
 */

#define ROMBasePtr0     (0x0<<10)                      /*=0x00000000*/
#define ROMBasePtr0_S   (0x100<<10)                    /*=0x01000000*/
#define ROMEndPtr0      ((ROM_SIZE>>12)<<20)           /*=0x00200000*/
#define ROMEndPtr0_S    (((ROM_SIZE>>12)+0x100)<<20)   /*=0x01200000*/
#define PMC0            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/
#define rTpa0           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/
#define rTacc0          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/
#define rROMCON0        (ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0)
#define rROMCON0_S      (ROMEndPtr0_S+ROMBasePtr0_S+rTacc0+rTpa0+PMC0)

/***************************************************************************
 * -> ROMCON1 : ROM Bank1 Control register, Mailbox Interface
 */

#define ROMBasePtr1     (0x3fc<<10)                 /*=0x0fc0000*/
#define ROMEndPtr1      ((0xfd0000>>12)<<20)        /*=0x0fd0000*/
#define PMC1            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/
#define rTpa1           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/
#define rTacc1          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/
#define rROMCON1        (ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1)

/***************************************************************************
 * -> ROMCON2 : ROM Bank2 Control register, EEPROM
 */

#define ROMBasePtr2     (0x3fb<<10)                 /*=0x0fb0000*/
#define ROMEndPtr2      ((0xfc0000>>12)<<20)       /*=0x0fc0000*/
#define PMC2            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/
#define rTpa2           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/
#define rTacc2          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/
#define rROMCON2        (ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2)

/***************************************************************************
 * -> ROMCONx : unused ROM Bank Control registers
 */

#define rROMCON3      0x60