hd_rmv.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

     tmp_dat_d1 <= #D tmp_dat;
     tmp_dat_d2 <= #D tmp_dat_d1;
     tmp_dat_d3 <= #D tmp_dat_d2;
     tmp_dat_d4 <= #D tmp_dat_d3;
  end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     vld_cnt <= #D 4'b0001;
  else if(~sop_sys_n)
     vld_cnt <= #D 4'b0001;
  else if(~dvld_sys_n)
     vld_cnt <= #D {vld_cnt[2:0],vld_cnt[3]};
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
  begin
     sop <= #D 1'b0;
     eop <= #D 1'b0;
     vld <= #D 1'b0;
     err <= #D 1'b0;
  end
  else
  begin
     sop <= #D tmp_sop && vld_cnt[3];
     eop <= #D tmp_eop && tmp_vld;
     vld <= #D (tmp_vld && vld_cnt[3]) || (tmp_vld && tmp_eop);
     err <= #D 1'b0;
  end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     dat <= #D 32'b0;
  else if(tmp_eop && tmp_vld)
     case(1'b1)
        vld_cnt[0]:   dat <= #D {tmp_dat,24'b0};
        vld_cnt[1]:   dat <= #D {tmp_dat_d1,tmp_dat,16'b0};
        vld_cnt[2]:   dat <= #D {tmp_dat_d2,tmp_dat_d1,tmp_dat,8'b0};
        vld_cnt[3]:   dat <= #D {tmp_dat_d3,tmp_dat_d2,tmp_dat_d1,tmp_dat};
        default   :   dat <= #D {tmp_dat_d3,tmp_dat_d2,tmp_dat_d1,tmp_dat};
      endcase
   else
      dat <= #D {tmp_dat_d3,tmp_dat_d2,tmp_dat_d1,tmp_dat};
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     mod <= #D 2'b0;
  else if(tmp_eop && tmp_vld)
     case(1'b1)
        vld_cnt[0]:   mod <= #D 2'b11;
        vld_cnt[1]:   mod <= #D 2'b10;
        vld_cnt[2]:   mod <= #D 2'b01;
        vld_cnt[3]:   mod <= #D 2'b00;
        default: mod <= #D 2'b0;
      endcase
   else
      mod <= #D 2'b0;
end
/*-----------------------------------------------------*\
                remove ISL protocol
\*-----------------------------------------------------*/

//judge the ISL header
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     sop_d1 <= #D 1'b0;
  else if(sop && vld)
     sop_d1 <= #D 1'b1;
  else if(vld)
     sop_d1 <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     isl_flag_h <= #D 1'b0;
  else if(eop && vld)
     isl_flag_h <= #D 1'b0;
  else if(sop && vld && dat[31:26] == ISL_0 && dat[24:16] == ISL_1[32:24])
     isl_flag_h <= #D 1'b1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     isl_flag_m <= #D 1'b0;
  else if(eop && vld)
     isl_flag_m <= #D 1'b0;
  else if(sop && vld && dat[15:0] == ISL_1[23:8])
     isl_flag_m <= #D 1'b1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     isl_flag_l <= #D 1'b0;
  else if(eop && vld)
     isl_flag_l <= #D 1'b0;
  else if(sop_d1 && vld && dat[31:24] == ISL_1[7:0])
     isl_flag_l <= #D 1'b1;
end

assign isl_flag = isl_flag_h && isl_flag_m && isl_flag_l;

//delay the input signal
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n)
     begin 
       dat_d1 <= #D 32'b0;
       dat_d2 <= #D 32'b0;
     end
  else if(vld || eop_d1)
     begin
       dat_d1 <= #D dat;
       dat_d2 <= #D dat_d1;
     end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     begin
       eop_d1 <= #D 1'b0;
       eop_d2 <= #D 1'b0;
     end
  else
     begin
       eop_d1 <= #D eop && vld;
       eop_d2 <= #D eop_d1;
     end  
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     begin
       err_d1 <= #D 1'b0;
       err_d2 <= #D 1'b0;
     end
  else
     begin
       err_d1 <= #D eop && vld && err;
       err_d2 <= #D err_d1;
     end  
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       mod_d1 <= #D 2'b0;
  else if(eop && vld)
       mod_d1 <= #D mod;
  else
       mod_d1 <= #D 2'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     mod_d2 <= #D 2'b0;
  else
     mod_d2 <= #D mod_d1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     begin
       isl_flag_d1 <= #D 1'b0;
       isl_flag_d2 <= #D 1'b0;
     end
  else
     begin
       isl_flag_d1 <= #D eop && vld && isl_flag;
       isl_flag_d2 <= #D isl_flag_d1;
     end
end

//remove the ISL header
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     isl_cnt <= #D 4'b0;
  else if(sop && vld)
     isl_cnt <= #D 4'b1;
  else if(eop && vld)
     isl_cnt <= #D 4'b0;
  else if(&isl_cnt)
     isl_cnt <= #D isl_cnt;
  else if(vld)
     isl_cnt <= #D isl_cnt + 4'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     risl_done_sop <= #D 1'b0;
  else if((~isl_flag && isl_cnt == 4'd2 || isl_flag && isl_cnt == 4'd8) && vld)
     risl_done_sop <= #D 1'b1;
  else
     risl_done_sop <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     risl_done_eop <= #D 1'b0;
  else if(~isl_flag_d2 && eop_d2 || isl_flag_d1 && eop_d1 && ~mod_d1[1] ||isl_flag&&
          eop && vld && mod[1])
     risl_done_eop <= #D 1'b1;
  else
     risl_done_eop <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tran_flag <= #D 1'b0;
  else if((~isl_flag && isl_cnt == 4'd2 || isl_flag && isl_cnt == 4'd8) && vld)
     tran_flag <= #D 1'b1;
  else if(~isl_flag_d2 && eop_d2 || isl_flag_d1 && eop_d1 && ~mod_d1[1] || isl_flag && 
          eop && vld && mod[1])
     tran_flag <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     risl_done_vld <= #D 1'b0;
  else if((~isl_flag && isl_cnt == 4'd2 || isl_flag && isl_cnt == 4'd8) && vld)
     risl_done_vld <= #D 1'b1;
  else
     risl_done_vld <= #D tran_flag && (vld || eop_d1 || eop_d2);
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     risl_done_mod <= #D 2'b0;
  else if(isl_flag && eop && vld && mod[1])
     risl_done_mod <= #D {1'b0,mod[0]};
  else if(isl_flag_d1 && eop_d1 && ~mod[1])
     risl_done_mod <= #D {1'b1,mod_d1[0]};
  else if(~isl_flag_d2 && eop_d2)
     risl_done_mod <= #D mod_d2;
  else
     risl_done_mod <= #D 2'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     risl_done_dat <= #D 32'b0;
  else if(isl_flag && vld || isl_flag_d1 && eop_d1 || isl_flag_d2 && eop_d2)
     risl_done_dat <= #D {dat_d2[15:0],dat_d1[31:16]};
  else
     risl_done_dat <= #D dat_d2;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     risl_done_err <= #D 1'b0;
  else if(~isl_flag_d2 && err_d2 || isl_flag_d1 && err_d1 && ~mod_d1[1] ||isl_flag&&
          eop && vld && err)
     risl_done_err <= #D 1'b1;
  else
     risl_done_err <= #D 1'b0;     
end

/*-----------------------------------------------------*\
                remove VLAN & MPLS
\*-----------------------------------------------------*/

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     begin
       done_dat <= #D 32'b0;
       done_sop <= #D 1'b0;
       done_eop <= #D 1'b0;
       done_mod <= #D 2'b0;
       done_vld <= #D 1'b0;
       done_err <= #D 1'b0;       
     end
  else
     begin
       done_dat <= #D risl_done_dat;
       done_sop <= #D risl_done_sop;
       done_eop <= #D risl_done_eop;
       done_mod <= #D risl_done_mod;
       done_vld <= #D risl_done_vld;
       done_err <= #D risl_done_err;
     end
end
                    
always @(posedge sys_clk or negedge sys_rst_n)
begin               
  if(!sys_rst_n)    
     eth_cnt <= #D 2'd0;
  else if(risl_done_sop && risl_done_vld)
     eth_cnt <= #D 2'd1;
  else if(eth_cnt == 2'd0)
     eth_cnt <= #D 2'd0;
  else if(risl_done_vld)
     eth_cnt <= #D eth_cnt + 2'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     vlan_flag <= #D 1'b0;
  else if(eth_cnt == 2'd3 && risl_done_vld && risl_done_dat[31:16] == VLAN)
     vlan_flag <= #D 1'b1;
  else if(risl_done_vld)
     vlan_flag <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     mpls_flag_u <= #D 1'b0;
  else if((eth_cnt == 2'd3 || vlan_flag) && risl_done_vld && risl_done_dat[31:16] == MPLS_U)
     mpls_flag_u <= #D 1'b1;
  else if(risl_done_vld && risl_done_dat[24])
     mpls_flag_u <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     mpls_flag_m <= #D 1'b0;
  else if((eth_cnt == 2'd3 || vlan_flag) && risl_done_vld && risl_done_dat[31:16] == MPLS_M)
     mpls_flag_m <= #D 1'b1;
  else if(risl_done_vld && risl_done_dat[24])
     mpls_flag_m <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     begin
       mpls_flag_u_d <= #D 1'b0;
       mpls_flag_m_d <= #D 1'b0;
     end
  else
     begin
       mpls_flag_u_d <= #D mpls_flag_u;
       mpls_flag_m_d <= #D mpls_flag_m;
     end
end

//send packet to cal
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     begin
       rmv_sop_cal <= #D 1'b0;
       rmv_eop_cal <= #D 1'b0;
       rmv_err_cal <= #D 1'b0;
       rmv_mod_cal <= #D 2'b0;
     end
  else
     begin
       rmv_sop_cal <= #D done_sop;
       rmv_eop_cal <= #D done_eop;
       rmv_err_cal <= #D done_err;
       rmv_mod_cal <= #D done_mod;
     end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     rmv_vld_cal <= #D 1'b0;
  else
     rmv_vld_cal <= #D done_vld && ~(vlan_flag || 
                       mpls_flag_u || mpls_flag_m);
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     rmv_dat_cal[31:16] <= #D 16'b0;
  else if(~mpls_flag_u && mpls_flag_u_d || 
          ~mpls_flag_m && mpls_flag_m_d)
     rmv_dat_cal[31:16] <= #D IP;    
  else
     rmv_dat_cal[31:16] <= #D  done_dat[31:16];
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     rmv_dat_cal[15:0] <= #D 16'b0;
  else
     rmv_dat_cal[15:0] <= #D done_dat[15:0];
end

endmodule