hd_rmv.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

//remove isl vlan mpls header
//-----------------------------------------------------------------------------
// Title      : header remove modle
// Project    : 
//-----------------------------------------------------------------------------
// File       : hd_rmv.v
// Author     : 
// Date       : 07-10-20
//-----------------------------------------------------------------------------
// Description: 
//
//-------------------------------------------------------------------------------

`timescale 1ns/10ps

module hd_rmv(
sys_clk,
rx_clk,
sys_rst_n,
rd_data_out,   
rd_sof_n,  
rd_eof_n,
rd_src_rdy_n,  
rd_dst_rdy_n, 
rx_fifo_status,
rmv_sop_cal,  
rmv_eop_cal,  
rmv_vld_cal,  
rmv_err_cal,  
rmv_dat_cal,  
rmv_mod_cal,  
cal_afull_rmv
);

//---------------------------------------------------------------------------
// parameter definition
//---------------------------------------------------------------------------

parameter   D = 2;
parameter   [5:0]  ISL_0 = 6'h00;
parameter   [32:0] ISL_1 = 33'h1_000c_0000;
parameter   VLAN    = 16'h8100;
parameter   MPLS_U  = 16'h8847;
parameter   MPLS_M  = 16'h8848;
parameter   IP      = 16'h0800;

//---------------------------------------------------------------------------
// input output port
//---------------------------------------------------------------------------

//Global Signals
input               sys_clk;
input               sys_rst_n;

input               rx_clk;
// Client Fifo Interface
input  [7:0]        rd_data_out;
input               rd_sof_n;
input               rd_eof_n;
input               rd_src_rdy_n;
output              rd_dst_rdy_n;
input  [3:0]        rx_fifo_status;

//calculat Interface
output              rmv_sop_cal;
output              rmv_eop_cal;
output              rmv_vld_cal;
output              rmv_err_cal;
output    [31:0]    rmv_dat_cal;
output    [1:0]     rmv_mod_cal;
input               cal_afull_rmv;

//---------------------------------------------------------------------------
// Define Internal Signals
//---------------------------------------------------------------------------
reg  wen;
reg  [5:0] waddr;
reg  [5:0] raddr;
reg  [9:0] wdat;
wire [9:0] rdat;
reg  fifo_empty_n;
wire  ren;
reg [5:0] raddr_gray;
reg [5:0] raddr_wd_1;
reg [5:0] raddr_wd_2;
reg [5:0] raddr_wd_b;
reg [5:0] frame;
reg [5:0] waddr_gray;
reg [5:0] waddr_rd_1;
reg [5:0] waddr_rd_2;
reg [5:0] waddr_rd_b;
wire [5:0] raddr_next;
reg data_write;
wire [9:0] data_in;
wire [9:0] data_out;
wire lb_empty_n;
wire lb_afull;
wire  data_read;
reg  dvld_sys_n;
reg  sop_sys_n;
reg  eop_sys_n;
reg [7:0] dat_sys_n;
reg       rd_dst_rdy_n;
reg tmp_sop;
reg tmp_eop;
reg tmp_vld;
reg  [7:0] tmp_dat;
reg  [7:0] tmp_dat_d1;
reg  [7:0] tmp_dat_d2;
reg  [7:0] tmp_dat_d3;
reg  [7:0] tmp_dat_d4;
reg  [3:0] vld_cnt;
reg  sop;
reg  eop;
reg  vld;
reg [31:0] dat;
reg  err;
reg [1:0] mod;
reg  sop_d1;
reg isl_flag_h;
reg isl_flag_m;
reg isl_flag_l;
wire  isl_flag;
reg [31:0]  dat_d1;
reg [31:0]  dat_d2;
reg  eop_d1;
reg  eop_d2;
reg  err_d1;
reg  err_d2;
reg  [1:0] mod_d1;
reg  [1:0] mod_d2;
reg  isl_flag_d1;
reg  isl_flag_d2;
reg  [3:0] isl_cnt;
reg  risl_done_sop;
reg  risl_done_eop;
reg  tran_flag;
reg  risl_done_vld;
reg  [1:0] risl_done_mod;
reg  [31:0] risl_done_dat;
reg  risl_done_err;
reg	[1:0]	eth_cnt;
reg		vlan_flag;
reg		mpls_flag_u;
reg		mpls_flag_m;
reg		mpls_flag_u_d;
reg		mpls_flag_m_d;
reg     [31:0]  done_dat;
reg             done_sop;
reg             done_eop;
reg     [1:0]   done_mod;
reg             done_vld;
reg             done_err;
reg    rmv_sop_cal;
reg    rmv_eop_cal;
reg    rmv_err_cal;
reg    rmv_vld_cal;
reg [1:0]   rmv_mod_cal;
reg [31:0]  rmv_dat_cal;
//---------------------------------------------------------------------------
// Main Code
//---------------------------------------------------------------------------
//convert rx_clk to sys_clk
always @(posedge rx_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     wen <= #D 1'b0;
  else
     wen <= #D ~rd_src_rdy_n && ~rd_dst_rdy_n;
end

always @(posedge rx_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     waddr <= #D 6'b0;
  else if(wen)
     waddr <= #D waddr + 6'd1;
end

always @(posedge rx_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     wdat <= #D 10'b0;
  else
     wdat <= #D {rd_sof_n,rd_eof_n,rd_data_out};
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       raddr_gray <= #D 6'b0;    
    else
       raddr_gray <= #D raddr ^ (raddr >> 1);
end

always @(posedge rx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         raddr_wd_1 <= #D 6'b0;
         raddr_wd_2 <= #D 6'b0;
       end    
    else
       begin
         raddr_wd_1 <= #D raddr_gray;
         raddr_wd_2 <= #D raddr_wd_1;
       end
end

always @(posedge rx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         raddr_wd_b[0] <= #D 1'b0;
         raddr_wd_b[1] <= #D 1'b0;
         raddr_wd_b[2] <= #D 1'b0;
         raddr_wd_b[3] <= #D 1'b0;
         raddr_wd_b[4] <= #D 1'b0;
         raddr_wd_b[5] <= #D 1'b0;
       end   
    else
       begin
         raddr_wd_b[0] <= #D ^raddr_wd_2;
         raddr_wd_b[1] <= #D ^(raddr_wd_2>>1);
         raddr_wd_b[2] <= #D ^(raddr_wd_2>>2);
         raddr_wd_b[3] <= #D ^(raddr_wd_2>>3);
         raddr_wd_b[4] <= #D ^(raddr_wd_2>>4);
         raddr_wd_b[5] <= #D ^(raddr_wd_2>>5);
       end     
end

always @(posedge rx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       frame <= #D 6'b0;    
    else
       frame <= #D waddr - raddr_wd_b;
end

always @(posedge rx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       rd_dst_rdy_n <= #D 1'b0;
    else if(frame > 6'd40)
       rd_dst_rdy_n <= #D 1'b1;
    else if(frame < 6'd30)
       rd_dst_rdy_n <= #D 1'b0;
end

dpram64x10 u_dpram64x10(
    .addra (waddr),
    .addrb (raddr),
    .clka  (rx_clk),
    .clkb  (sys_clk),
    .dina  (wdat),
    .doutb (rdat),
    .enb   (ren),
    .wea   (wen)
    );

always @(posedge rx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       waddr_gray <= #D 6'b0;
    else
       waddr_gray <= #D waddr ^ (waddr>>1);
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         waddr_rd_1 <= #D 6'b0;
         waddr_rd_2 <= #D 6'b0;
       end     
    else
       begin
         waddr_rd_1 <= #D waddr_gray;
         waddr_rd_2 <= #D waddr_rd_1;
       end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         waddr_rd_b[0] <= #D 1'b0;
         waddr_rd_b[1] <= #D 1'b0;
         waddr_rd_b[2] <= #D 1'b0;
         waddr_rd_b[3] <= #D 1'b0;
         waddr_rd_b[4] <= #D 1'b0;
         waddr_rd_b[5] <= #D 1'b0;
       end   
    else
       begin
         waddr_rd_b[0] <= #D ^waddr_rd_2;
         waddr_rd_b[1] <= #D ^(waddr_rd_2>>1);
         waddr_rd_b[2] <= #D ^(waddr_rd_2>>2);
         waddr_rd_b[3] <= #D ^(waddr_rd_2>>3);
         waddr_rd_b[4] <= #D ^(waddr_rd_2>>4);
         waddr_rd_b[5] <= #D ^(waddr_rd_2>>5);
       end 
end

assign ren = fifo_empty_n && ~lb_afull;

assign raddr_next = (ren) ? raddr + 1 : raddr;

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       raddr <= #D 6'b0;    
    else
       raddr <= #D raddr_next;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       fifo_empty_n <= #D 1'b0;
    else if(waddr_rd_b == raddr_next)
       fifo_empty_n <= #D 1'b0;
    else
       fifo_empty_n <= #D 1'b1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       data_write <= #D 1'b0;
    else
       data_write <= #D ren;
end

assign data_in = rdat;

//instance lb_fifo_4cell
lb_fifo_4cell #(10,D) U_lb_fifo_4cell (
  .sys_clk      (sys_clk),
  .sys_rst_n    (sys_rst_n),
  .data_in      (data_in),
  .data_write   (data_write),
  .data_out     (data_out),
  .data_read    (data_read),
  .full_cell0   (lb_empty_n),
  .full_cell1   (),
  .full_cell2   (lb_afull),
  .full_cell3   ()
);

assign data_read = lb_empty_n && ~cal_afull_rmv;

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         sop_sys_n  <= #D 1'b1;
         eop_sys_n  <= #D 1'b1;
         dvld_sys_n <= #D 1'b1;
         dat_sys_n  <= #D 8'b0;
       end    
    else
       begin
         sop_sys_n  <= #D ~data_read || data_out[9];
         eop_sys_n  <= #D ~data_read || data_out[8];
         dvld_sys_n <= #D ~data_read;
         dat_sys_n  <= #D data_out[7:0];
       end
end

//------------process data-------//
//convert 8bit to 32bit word
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_sop <= #D 1'b0;
  else if(~sop_sys_n)
     tmp_sop <= #D 1'b1;
  else if(tmp_sop && vld_cnt[3])
     tmp_sop <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_eop <= #D 1'b0;
  else
     tmp_eop <= #D ~eop_sys_n;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_vld <= #D 1'b0;
  else
     tmp_vld <= #D ~dvld_sys_n;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
  begin
     tmp_dat    <= #D 8'b0;
     tmp_dat_d1 <= #D 8'b0;
     tmp_dat_d2 <= #D 8'b0;
     tmp_dat_d3 <= #D 8'b0;
     tmp_dat_d4 <= #D 8'b0;
  end
  else if (~dvld_sys_n)
  begin
     tmp_dat    <= #D dat_sys_n;