flow_sts.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

//flow statistic
//-----------------------------------------------------------------------------
// Title      : 
// Project    : 
//-----------------------------------------------------------------------------
// File       : flow_sts.v
// Author     : 
// Date       : 08-03-06
//-----------------------------------------------------------------------------
// Description: 
//
//-----------------------------------------------------------------------------

`timescale 1ns/10ps

module flow_sts(
sys_clk,
sys_rst_n,
pre_sop_fs,
pre_eop_fs,
pre_dat_fs, 
pre_mod_fs,
pre_dvld_fs,
fs_pb_pre,
fs_sop_key,
fs_eop_key,
fs_dat_key,
fs_mod_key,
fs_dvld_key,
key_pb_fs,
conf_wr_fs,
conf_rd_fs,
conf_clr_fs,
conf_wdat,
conf_addr,
fs_rdat_conf
);

/*-------------------------------------------------------------------*\
                          Parameter Description
\*-------------------------------------------------------------------*/

parameter D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

//global signal
input                sys_clk;
input                sys_rst_n;

//interface with pre
input                pre_sop_fs;
input                pre_eop_fs;
input     [31:0]     pre_dat_fs;
input     [1:0]      pre_mod_fs;
input                pre_dvld_fs;
output               fs_pb_pre;

//interface with drop
output               fs_sop_key;
output               fs_eop_key;
output   [31:0]      fs_dat_key;
output    [1:0]      fs_mod_key;
output               fs_dvld_key;
input                key_pb_fs;

//interface with cam_if
input               conf_wr_fs;
input               conf_rd_fs;
input               conf_clr_fs;
input    [15:0]     conf_wdat;
input    [3:0]      conf_addr;
output   [15:0]     fs_rdat_conf;

/*-------------------------------------------------------------------*\
                          Reg/Wire Description
\*-------------------------------------------------------------------*/
reg                 fs_pb_pre;
reg                 fs_sop_key;
reg                 fs_eop_key;
reg      [31:0]     fs_dat_key;
reg      [1:0]      fs_mod_key;
reg                 fs_dvld_key;
reg      [2:0]      eth_cnt;
reg      [7:0]      ip_cnt;
reg      [7:0]      sip_low;
reg      [7:0]      dip_low;
reg      [7:0]      sp_low;
reg      [7:0]      dp_low;
reg      [3:0]      sd_slect;
reg                 f1_vld;
reg                 f2_vld;
reg                 f1_eop;
reg                 f2_eop;
reg      [2:0]      vld_bytes;
reg      [10:0]     pkt_len_tmp;
reg      [9:0]      time_cnt_l;
reg      [9:0]      time_cnt_h;          
reg      [31:0]     time_stamp;
reg                 init_start;
reg                 init_en;
reg      [7:0]      init_addr;
reg                 divid;
reg      [10:0]     pkt_len;
reg                 pkt_rd_flag;
wire                pkt_rd_en;
reg                 pkt_rd_en_d1;
reg                 pkt_rd_en_d2;
reg                 pkt_rd_en_d3;
wire                pkt_wr_en;
wire     [79:0]     pkt_wdat;
reg      [7:0]      pkt_addr;
reg                 ppc_rd_start;
reg                 ppc_rd_flag;
wire                ppc_rd_en;
reg                 ppc_wr_en;
reg                 ppc_rd_en_d1;
reg                 ppc_rd_en_d2;
reg      [7:0]      ppc_addr;
reg      [31:0]     current_time;
reg      [79:0]     ppc_rdat;
reg      [15:0]     fs_rdat_conf;
reg      [7:0]      waddr;
reg      [79:0]     wdat;
reg                 wen;
wire     [79:0]     rdat;
reg                 ren;
reg      [7:0]      raddr;
/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/                           
//send push back to pre
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      fs_pb_pre <= #D 1'b0;
   else
      fs_pb_pre <= #D key_pb_fs;
end

//send packe to key_gen
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      begin
        fs_sop_key  <= #D 1'b0;
        fs_eop_key  <= #D 1'b0;
        fs_dat_key  <= #D 32'b0;
        fs_mod_key  <= #D 2'b0;
        fs_dvld_key <= #D 1'b0;
      end
   else
      begin
        fs_sop_key  <= #D pre_sop_fs;
        fs_eop_key  <= #D pre_eop_fs;
        fs_dat_key  <= #D pre_dat_fs;
        fs_mod_key  <= #D pre_mod_fs;
        fs_dvld_key <= #D pre_dvld_fs;
      end
end

//-----------------find sip and dip-------------------------//
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      eth_cnt <= #D 3'h0;
   else if(pre_sop_fs && pre_dvld_fs)
      eth_cnt <= #D 3'h1;
   else if(&eth_cnt)
      eth_cnt <= #D eth_cnt;
   else if(pre_dvld_fs)
      eth_cnt <= #D eth_cnt + 3'h1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ip_cnt <= #D 8'h80;
   else if(pre_dvld_fs && eth_cnt == 3'h2)
      ip_cnt <= #D 8'h1;
   else if(ip_cnt[7])
      ip_cnt <= #D ip_cnt;
   else if(pre_dvld_fs)
      ip_cnt <= #D ip_cnt << 1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      sip_low <= #D 8'b0;
   else if(ip_cnt[4] && pre_dvld_fs)
      sip_low <= #D pre_dat_fs[23:16];
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      dip_low <= #D 8'b0;
   else if(ip_cnt[5] && pre_dvld_fs)
      dip_low <= #D pre_dat_fs[23:16];
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      sp_low <= #D 8'b0;
   else if(ip_cnt[5] && pre_dvld_fs)
      sp_low <= #D pre_dat_fs[7:0];
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      dp_low <= #D 8'b0;
   else if(ip_cnt[6] && pre_dvld_fs)
      dp_low <= #D pre_dat_fs[23:16];
end

//sd_slect: 0001:select sip, 0010:select dip, 0100:select sp, 1000:select dp
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      sd_slect <= #D 4'b0;
   else if(conf_wr_fs && conf_addr == 4'b0)
      sd_slect <= #D conf_wdat[3:0];
end
//----------------- pkt len -------------------------------//
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      begin
        f1_vld  <= #D 1'b0;
        f2_vld  <= #D 1'b0;
        f1_eop  <= #D 1'b0;
        f2_eop  <= #D 1'b0;
      end
   else
      begin
        f1_vld  <= #D pre_dvld_fs;
        f2_vld  <= #D f1_vld;
        f1_eop  <= #D pre_eop_fs;
        f2_eop  <= #D f1_eop;
      end
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      vld_bytes <= #D 3'b0;
   else if(pre_eop_fs && pre_dvld_fs)
      case(pre_mod_fs)
        2'b00:   vld_bytes <= #D 3'b100;
        2'b01:   vld_bytes <= #D 3'b011;
        2'b10:   vld_bytes <= #D 3'b010;
        2'b11:   vld_bytes <= #D 3'b001;
        default: vld_bytes <= #D 3'b0;
      endcase
    else if(pre_dvld_fs)
       vld_bytes <= #D 3'b100;
    else 
       vld_bytes <= #D 3'b0;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      pkt_len_tmp <= #D 11'b0;
   else if(f2_eop && f2_vld)
      pkt_len_tmp <= #D 11'b0;
   else if(f1_vld)
      pkt_len_tmp <= #D pkt_len_tmp + vld_bytes;
end

//----------------- time ----------------------------------//
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      time_cnt_l <= #D 10'b0;
   else
      time_cnt_l <= #D time_cnt_l + 1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      time_cnt_h <= #D 10'b0;
   else if (time_cnt_l == 10'd1023)
      time_cnt_h <= #D time_cnt_h + 1;
end

//add 1 every 10ms, turn around every 1.36year
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      time_stamp <= #D 32'b0;
   else if (time_cnt_l == 10'd1023 && time_cnt_h == 10'd1023)
      time_stamp <= #D time_stamp + 1;
end

//-----------------initial ----------------------------------//
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      init_start <= #D 1'b0;
   else
      init_start <= #D conf_wr_fs && conf_addr == 4'b1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      init_en <= #D 1'b0;
   else if (init_start)
      init_en <= #D 1'b1;
   else if (init_addr == 8'hff)
   	  init_en <= #D 1'b0;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      init_addr <= #D 8'b0;
   else if (init_start)
   	  init_addr <= #D 8'b0;
   else if (init_en)
      init_addr <= #D init_addr + 8'b1;
end

//-----------------pkt access ----------------------------------//
//pkt access statistic memory when divid is 0, 
//power pc access statistic memory when divid is 1
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      divid <= #D 1'b0;
   else
   	  divid <= #D ~divid;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      pkt_len <= #D 11'b0;
   else if(f2_eop && f2_vld)
      pkt_len <= #D pkt_len_tmp;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      pkt_rd_flag <= #D 1'b0;
   else if (f2_eop && f2_vld)
      pkt_rd_flag <= #D 1'b1;
   else if (divid)
   	  pkt_rd_flag <= #D 1'b0;
end

assign pkt_rd_en = pkt_rd_flag && divid;

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
   	begin
      pkt_rd_en_d1 <= #D 1'b0;
      pkt_rd_en_d2 <= #D 1'b0;
      pkt_rd_en_d3 <= #D 1'b0;
    end
   else
   	begin
      pkt_rd_en_d1 <= #D pkt_rd_en;
      pkt_rd_en_d2 <= #D pkt_rd_en_d1;
      pkt_rd_en_d3 <= #D pkt_rd_en_d2;
    end
end

assign pkt_wr_en = pkt_rd_en_d2;

//always @ (posedge sys_clk or negedge sys_rst_n)
//begin
//   if(!sys_rst_n)
//      pkt_wdat <= #D 80'b0;
//   else if (pkt_rd_en_d2)//time  ,     byte  cnt       ,   packet cnt
//      pkt_wdat <= #D {rdat[79:48],rdat[47:21] + pkt_len,rdat[20:0] + 1};
//end
wire [26:0] new_len;
wire [20:0] new_pkt;
assign new_len = rdat[47:21] + pkt_len;
assign new_pkt = rdat[20:0] + 21'b1;
assign pkt_wdat = {rdat[79:48],new_len,new_pkt};

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      pkt_addr <= #D 8'b0;
   else if (sd_slect[0])
      pkt_addr <= #D sip_low;
   else if (sd_slect[1])
   	  pkt_addr <= #D dip_low;
   else if (sd_slect[2])
   	  pkt_addr <= #D sp_low;
   else if (sd_slect[3])
   	  pkt_addr <= #D dp_low;
   else
   	  pkt_addr <= #D sip_low;
end
//-----------------ppc access ----------------------------------//
//pkt access statistic memory when divid is 0, 
//power pc access statistic memory when divid is 1
always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ppc_rd_start <= #D 1'b0;
   else
      ppc_rd_start <= #D conf_wr_fs && conf_addr == 4'd2;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ppc_rd_flag <= #D 1'b0;
   else if (ppc_rd_start)
      ppc_rd_flag <= #D 1'b1;
   else if (~divid)
   	  ppc_rd_flag <= #D 1'b0;
end

assign ppc_rd_en = ppc_rd_flag && ~divid;

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ppc_wr_en <= #D 1'b0;
   else
      ppc_wr_en <= #D ppc_rd_en_d1;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ppc_addr <= #D 8'b0;
   else if (conf_wr_fs && conf_addr == 4'd2)
      ppc_addr <= #D conf_wdat[7:0];
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
   	begin
      ppc_rd_en_d1 <= #D 1'b0;
      ppc_rd_en_d2 <= #D 1'b0;
    end
   else
   	begin
      ppc_rd_en_d1 <= #D ppc_rd_en;
      ppc_rd_en_d2 <= #D ppc_rd_en_d1;
    end
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      current_time <= #D 32'b0;
   else if (ppc_rd_en)
      current_time <= #D time_stamp;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      ppc_rdat <= #D 80'b0;
   else if (ppc_rd_en_d2)
      ppc_rdat <= #D rdat;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     fs_rdat_conf <= #D 16'b0;
  else if(conf_rd_fs)
  begin
    case(conf_addr)
    4'd0:    fs_rdat_conf <= #D {12'b0,sd_slect};
    4'd3:    fs_rdat_conf <= #D ppc_rdat[79:64];
    4'd4:    fs_rdat_conf <= #D ppc_rdat[63:48];
    4'd5:    fs_rdat_conf <= #D ppc_rdat[47:32];
    4'd6:    fs_rdat_conf <= #D ppc_rdat[31:16];
    4'd7:    fs_rdat_conf <= #D ppc_rdat[15:0];
    4'd8:    fs_rdat_conf <= #D current_time[31:16];
    4'd9:    fs_rdat_conf <= #D current_time[15:0];
    default: fs_rdat_conf <= #D 16'b0;
    endcase
  end
end
//----------------dpram interface ------------------------------//

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      waddr <= #D 8'b0;
   else if (init_en)
      waddr <= #D init_addr;
   else if (pkt_wr_en)
   	  waddr <= #D pkt_addr;
   else if (ppc_wr_en)
   	  waddr <= #D ppc_addr;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      wdat <= #D 80'b0;
   else if (init_en)
      wdat <= #D 80'b0;
   else if (pkt_wr_en)
   	  wdat <= #D pkt_wdat;
   else if (ppc_wr_en)
   	  wdat <= #D {current_time,48'b0};
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
   if(!sys_rst_n)
      wen <= #D 1'b0;
   else if (init_en)
      wen <= #D 1'b1;
   else if (pkt_wr_en)
   	  wen <= #D 1'b1;
   else if (ppc_wr_en)
   	  wen <= #D 1'b1;
   else
   	  wen <= #D 1'b0;
end

//instance dpram256x80
dpram256x80 u_dpram256x80(
    .addra (waddr),
    .addrb (raddr),
    .clka  (sys_clk),
    .clkb  (sys_clk),
    .dina  (wdat),
    .doutb (rdat),
    .enb   (ren),
    .wea   (wen)
    );

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     ren <= #D 1'b0;
  else if(pkt_rd_en)
     ren <= #D 1'b1;
  else if (ppc_rd_en)
  	 ren <= #D 1'b1;
  else
  	 ren <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     raddr <= #D 8'b0;
  else if(pkt_rd_en)
     raddr <= #D pkt_addr;
  else if (ppc_rd_en)
  	 raddr <= #D ppc_addr;
end

endmodule