clk_mod.v

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//
//-----------------------------------------------------------------------------
// Title      : The user logic top
// Project    : 
//-----------------------------------------------------------------------------
// File       : top.v
// Author     : 
// Date       : 08-03-11
//-----------------------------------------------------------------------------
// Description: 
//
//-----------------------------------------------------------------------------

`timescale 1ns/10ps

module clk_mod(
sys_clk_in,
sys_rst_n_in,
sys_clk_25m,
sys_clk_100m,
sys_rst_n
);

input             sys_clk_in;
input             sys_rst_n_in;

output            sys_clk_25m;
output            sys_clk_100m;
output            sys_rst_n;

wire		  tmp_rst_n;

dcm_25m u_dcm_25m(
               .CLKIN_IN        (sys_clk_in),
               .CLKFX_OUT       (sys_clk_25m),
               .CLKIN_IBUFG_OUT (),
               .LOCKED_OUT      ()
);

dcm_100m u_dcm_100m(
                .CLKIN_IN         (sys_clk_in),
                .CLKFX_OUT        (sys_clk_100m),
                .CLKIN_IBUFG_OUT  (), 
                .LOCKED_OUT       ()
);

assign tmp_rst_n = sys_rst_n_in;

BUFG bufg_reset_n (.I(tmp_rst_n), .O(sys_rst_n));

endmodule