drop.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

  if(!sys_rst_n) 
     waddr <= #D 10'b0;
  else if(drp_pkt)
     waddr <= #D tmp_waddr;
  else if(wen)
     waddr <= #D waddr + 10'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     tmp_waddr <= #D 10'b0;
  else if(~drp_pkt && tmp_eop_d)
     tmp_waddr <= #D waddr + 10'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     wdat <= #D 36'b0;
  else
     wdat <= #D {tmp_sop,tmp_eop,tmp_mod,tmp_dat};
end

//instance dpram1024x36
dpram1024x36 u_dpram1024x36(
    .addra (waddr),
    .addrb (raddr),
    .clka  (sys_clk),
    .clkb  (sys_clk),
    .dina  (wdat),
    .doutb (rdat),
    .enb   (ren),
    .wea   (wen)
    );

assign fifo_empty = tmp_waddr == raddr;

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     disp_addr <= #D 10'b0;
  else
     disp_addr <= #D waddr - raddr;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     afull <= #D 1'b0;
  else if(disp_addr[9:5] >= 5'b1_1111)
     afull <= #D 1'b1;
  else if(disp_addr[9:5] <= 5'b1_1101)
     afull <= #D 1'b0; 
end

//write to lb_fifo_5cell
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     use_frm <= #D 10'b0;
  else
     use_frm <= #D tmp_waddr - raddr;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     read_en <= #D 1'b1;
  else if(use_frm < 10'd4)
     read_en <= #D ~read_en;
  else
     read_en <= #D 1'b1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     ren <= #D 1'b0;
  else
     ren <= #D read_en && ~fifo_empty && ~lb_5cell_afull;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     raddr <= #D 10'b0;
  else if(ren)
     raddr <= #D raddr + 10'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     data_write <= #D 1'b0;
  else
     data_write <= #D ren;
end

assign data_in = rdat;

//instance lb_fifo_5cell
lb_fifo_5cell #(36,D) u_lb_fifo_5cell (
    .sys_clk    (sys_clk),     
    .sys_rst_n  (sys_rst_n),    
    .data_in    (data_in),
    .data_read  (data_read),    
    .data_out   (data_out),
    .data_write (data_write),   

    .full_cell0 (lb_5cell_empty_n), 
    .full_cell1 (),             
    .full_cell2 (lb_5cell_afull),    
    .full_cell3 (),
    .full_cell4 ()            
    );

//read from the lb_fifo_5cell
assign data_read = lb_5cell_empty_n && div_cnt[3] && ~ofifo_afull_cal;//??

assign vld_1 = data_read;
assign eop_1 = data_out[34] && data_read;
assign mod_1 = data_read ? data_out[33:32] : 2'b0;

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     vld_2 <= #D 1'b0;
  else if(eop_1 && mod_1 == 2'b11)
     vld_2 <= #D 1'b0;
  else
     vld_2 <= #D vld_1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
  begin
     eop_2 <= #D 1'b0;
     mod_2 <= #D 2'b0;
  end
  else
  begin
     eop_2 <= #D eop_1;
     mod_2 <= #D mod_1;
  end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     vld_3 <= #D 1'b0;
  else if(eop_2 && mod_2 == 2'b10)
     vld_3 <= #D 1'b0;
  else
     vld_3 <= #D vld_2;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
  begin
     eop_3 <= #D 1'b0;
     mod_3 <= #D 2'b0;
  end
  else
  begin
     eop_3 <= #D eop_2;
     mod_3 <= #D mod_2;
  end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     vld_4 <= #D 1'b0;
  else if(eop_3 && mod_3 == 2'b01)
     vld_4 <= #D 1'b0;
  else
     vld_4 <= #D vld_3;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
  begin
     eop_4 <= #D 1'b0;
     mod_4 <= #D 2'b0;
  end
  else
  begin
     eop_4 <= #D eop_3;
     mod_4 <= #D mod_3;
  end
end

assign eop = eop_1 && mod_1 == 2'b11 || eop_2 && mod_2 == 2'b10 || eop_3 && mod_3 == 2'b01 || eop_4 && mod_4 == 2'b00;
assign sop = data_read && data_out[35];
assign vld = vld_1 || vld_2 || vld_3 || vld_4;

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
  begin
     sop_d1 <= #D 1'b0;
     vld_d1 <= #D 1'b0;
     eop_d1 <= #D 1'b0;
     div_cnt_d1 <= #D 4'b0;
  end
  else
  begin
     sop_d1 <= #D sop;
     vld_d1 <= #D vld;
     eop_d1 <= #D eop;
     div_cnt_d1 <= #D div_cnt;
  end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     dat_d1 <= #D 32'b0;
  else if(data_read)
     dat_d1 <= #D data_out[31:0];
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
  begin
     sop_d2 <= #D 1'b0;
     vld_d2 <= #D 1'b0;
     eop_d2 <= #D 1'b0;
  end
  else
  begin
     sop_d2 <= #D sop_d1;
     vld_d2 <= #D vld_d1;
     eop_d2 <= #D eop_d1;
  end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     dat_d2 <= #D 8'b0;
  else if(div_cnt_d1[3])
     dat_d2 <= #D dat_d1[31:24];
  else if(div_cnt_d1[2])
     dat_d2 <= #D dat_d1[23:16];
  else if(div_cnt_d1[1])
     dat_d2 <= #D dat_d1[15:8];
  else if(div_cnt_d1[0])
     dat_d2 <= #D dat_d1[7:0];
end
/*---------------------------------------------*\
//divide 32bit packet to 8bit packet
\*---------------------------------------------*/

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     div_cnt <= #D 4'b1000;
  else if (eop)
     div_cnt <= #D 4'b1000;
  else if (vld)
     div_cnt <= #D {div_cnt[0],div_cnt[3:1]};
end

/*---------------------------------------------*\
//send packet out
\*---------------------------------------------*/
//convert rx_clk to sys_clk
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     ofifo_wen <= #D 1'b0;
  else
     ofifo_wen <= #D vld_d2;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     ofifo_waddr <= #D 6'b0;
  else if(ofifo_wen)
     ofifo_waddr <= #D ofifo_waddr + 6'd1;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     ofifo_wdat <= #D 10'b0;
  else
     ofifo_wdat <= #D {sop_d2,eop_d2,dat_d2};
end

always @(posedge tx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       raddr_gray <= #D 6'b0;    
    else
       raddr_gray <= #D ofifo_raddr ^ (ofifo_raddr >> 1);
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         raddr_wd_1 <= #D 6'b0;
         raddr_wd_2 <= #D 6'b0;
       end    
    else
       begin
         raddr_wd_1 <= #D raddr_gray;
         raddr_wd_2 <= #D raddr_wd_1;
       end
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         raddr_wd_b[0] <= #D 1'b0;
         raddr_wd_b[1] <= #D 1'b0;
         raddr_wd_b[2] <= #D 1'b0;
         raddr_wd_b[3] <= #D 1'b0;
         raddr_wd_b[4] <= #D 1'b0;
         raddr_wd_b[5] <= #D 1'b0;
       end   
    else
       begin
         raddr_wd_b[0] <= #D ^raddr_wd_2;
         raddr_wd_b[1] <= #D ^(raddr_wd_2>>1);
         raddr_wd_b[2] <= #D ^(raddr_wd_2>>2);
         raddr_wd_b[3] <= #D ^(raddr_wd_2>>3);
         raddr_wd_b[4] <= #D ^(raddr_wd_2>>4);
         raddr_wd_b[5] <= #D ^(raddr_wd_2>>5);
       end     
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       frame <= #D 6'b0;
    else
       frame <= #D ofifo_waddr - raddr_wd_b;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       ofifo_afull_cal <= #D 1'b0;
    else if(frame > 6'd40)
       ofifo_afull_cal <= #D 1'b1;
    else if(frame < 6'd30)
       ofifo_afull_cal <= #D 1'b0;
end

dpram64x10 u_dpram64x10(
    .addra (ofifo_waddr),
    .addrb (ofifo_raddr),
    .clka  (sys_clk),
    .clkb  (tx_clk),
    .dina  (ofifo_wdat),
    .doutb (ofifo_rdat),
    .enb   (ofifo_ren),
    .wea   (ofifo_wen)
    );

always @(posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       waddr_gray <= #D 6'b0;
    else
       waddr_gray <= #D ofifo_waddr ^ (ofifo_waddr>>1);
end

always @(posedge tx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         waddr_rd_1 <= #D 6'b0;
         waddr_rd_2 <= #D 6'b0;
       end
    else
       begin
         waddr_rd_1 <= #D waddr_gray;
         waddr_rd_2 <= #D waddr_rd_1;
       end
end

always @(posedge tx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       begin
         waddr_rd_b[0] <= #D 1'b0;
         waddr_rd_b[1] <= #D 1'b0;
         waddr_rd_b[2] <= #D 1'b0;
         waddr_rd_b[3] <= #D 1'b0;
         waddr_rd_b[4] <= #D 1'b0;
         waddr_rd_b[5] <= #D 1'b0;
       end   
    else
       begin
         waddr_rd_b[0] <= #D ^waddr_rd_2;
         waddr_rd_b[1] <= #D ^(waddr_rd_2>>1);
         waddr_rd_b[2] <= #D ^(waddr_rd_2>>2);
         waddr_rd_b[3] <= #D ^(waddr_rd_2>>3);
         waddr_rd_b[4] <= #D ^(waddr_rd_2>>4);
         waddr_rd_b[5] <= #D ^(waddr_rd_2>>5);
       end 
end

//read the data from the afifo
assign ofifo_ren = ofifo_empty_n && ~ofifo_lb_afull;

assign raddr_next = ofifo_ren ? ofifo_raddr + 1 : ofifo_raddr;

always @(posedge tx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       ofifo_raddr <= #D 6'b0;
    else
       ofifo_raddr <= #D raddr_next;
end

always @(posedge tx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       ofifo_empty_n <= #D 1'b0;
    else if(waddr_rd_b == raddr_next)
       ofifo_empty_n <= #D 1'b0;
    else
       ofifo_empty_n <= #D 1'b1;
end

always @(posedge tx_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
       ofifo_data_write <= #D 1'b0;
    else
       ofifo_data_write <= #D ofifo_ren;
end

assign ofifo_data_in = ofifo_rdat;

//instance lb_fifo_4cell
lb_fifo_4cell #(10,D) U_lb_fifo_4cell    (
  .sys_clk      (tx_clk),
  .sys_rst_n    (sys_rst_n),
  .data_in      (ofifo_data_in),
  .data_write   (ofifo_data_write),
  .data_out     (ofifo_data_out),
  .data_read    (ofifo_data_read),
  .full_cell0   (ofifo_lb_empty_n),
  .full_cell1   (),
  .full_cell2   (ofifo_lb_afull),
  .full_cell3   ()
);

assign ofifo_data_read = ofifo_lb_empty_n && ~wr_dst_rdy_n;

assign wr_sof_n = ~(ofifo_data_read && ofifo_data_out[9]);
assign wr_eof_n = ~(ofifo_data_read && ofifo_data_out[8]);
assign wr_src_rdy_n = ~ofifo_data_read;
assign wr_data = ofifo_data_out[7:0];

endmodule