drop.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

//drop the specified packets
//-----------------------------------------------------------------------------
// Title      : 
// Project    : 
//-----------------------------------------------------------------------------
// File       : drop.v
// Author     : 
// Date       : 07-11-2
//-----------------------------------------------------------------------------
// Description:
//
//-----------------------------------------------------------------------------

`timescale 1ns/10ps

module drop(
sys_clk,
tx_clk,
sys_rst_n,  
key_sop_drop,
key_eop_drop,
key_dat_drop,
key_mod_drop,
key_dvld_drop,
drop_pb_key,
ci_vld_drop,
ci_drp_drop,
ci_addr_drop,
ci_dat_drop,
wr_data,
wr_sof_n,
wr_eof_n,
wr_src_rdy_n,
wr_dst_rdy_n,
conf_wr_drop,
conf_rd_drop,
conf_clr_drop,
conf_addr_drop,
conf_wdat_drop,
drop_rdat_conf
);

/*-------------------------------------------------------------------*\
                          Parameter Description
\*-------------------------------------------------------------------*/
parameter D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

//   Global Signals
input		sys_clk;
input		sys_rst_n;

input   tx_clk;
//interface with key_gen
input           key_sop_drop;
input           key_eop_drop;
input  [31:0]   key_dat_drop;
input  [1:0]    key_mod_drop;
input           key_dvld_drop;
output          drop_pb_key;

//cam_if Interface
input           ci_vld_drop;
input           ci_drp_drop;
input  [7:0]    ci_addr_drop;
input  [3:0]    ci_dat_drop;

//mac interface
output  [7:0]   wr_data;
output          wr_sof_n;
output          wr_eof_n;
output          wr_src_rdy_n;
input           wr_dst_rdy_n;

//conf Interface
input		        conf_wr_drop;
input		        conf_rd_drop;
input		        conf_clr_drop;
input	 [3:0]	  conf_addr_drop;
input  [15:0]	  conf_wdat_drop;
output [15:0]   drop_rdat_conf;
/*-------------------------------------------------------------------*\
                          Reg/Wire Description
\*-------------------------------------------------------------------*/
reg             ram_wr_en;
reg   [8:0]     ram_wr_addr;
reg   [35:0]    ram_wr_data;
reg   [15:0]    in_pkt_cnt;
wire  [35:0]    ram_rd_data;
reg   [9:0]     ram_empty_cnt;
wire            ram_empty;
wire            ram_rd_en;
wire            lb_afull;
reg             ram_rd_en_d;
reg   [8:0]     ram_rd_addr;
reg   [8:0]     tmp_fifo_cnt;
reg             drop_pb_key;
wire            lb_wr_en;
reg             trans_flag;
wire            lb_rd_en;
reg   [12:0]    key_wr_data;
reg             key_wr_en;
wire            reg_fifo_with_data;
wire            reg_fifo_two_data;
wire            reg_fifo_key_afull;
wire            key_rd_en;
reg             tmp_sop;
reg             tmp_eop;
reg             tmp_eop_d;
reg             tmp_dvld;
reg   [1:0]     tmp_mod;
reg   [31:0]    tmp_dat;
reg             drp_pkt;
reg             wen;
reg   [9:0]     waddr;
reg   [9:0]     tmp_waddr;
reg   [35:0]    wdat;
wire  [35:0]    rdat;
wire            fifo_empty;
reg   [9:0]     disp_addr;
reg   [9:0]     use_frm;
reg             read_en;
reg             ren;
reg   [9:0]     raddr;
reg             data_write;
wire  [35:0]    data_in;
wire            data_read;
wire  [35:0]    data_out;
wire            lb_5cell_empty_n;
wire            lb_5cell_afull;
reg   [3:0]     div_cnt;
wire            sop;
wire            vld;
wire            eop;
wire             wr_sof_n;
wire             wr_eof_n;
wire             wr_src_rdy_n;
wire   [7:0]     wr_data;
reg   [15:0]    drop_rdat_conf;
wire  [35:0]    lb_rd_data;
wire  [12:0]    reg_rd_key;
reg             afull;

reg ofifo_wen;
reg [5:0]  ofifo_waddr;
reg [9:0]  ofifo_wdat;
wire [9:0] ofifo_rdat;
wire ofifo_ren;
reg [5:0] ofifo_raddr;
reg ofifo_afull_cal;
reg  [5:0] raddr_gray;
reg  [5:0] raddr_wd_1;
reg  [5:0] raddr_wd_2;
reg  [5:0] raddr_wd_b;
reg  [5:0] frame;
reg ofifo_empty_n;
reg ofifo_data_write;
wire [9:0] ofifo_data_in;
wire [9:0] ofifo_data_out;
reg [5:0] waddr_gray;
reg [5:0] waddr_rd_1;
reg [5:0] waddr_rd_2;
reg [5:0] waddr_rd_b;
wire [5:0] raddr_next;
wire ofifo_lb_afull;
wire ofifo_lb_empty_n;
wire ofifo_data_read;

wire vld_1;
reg  vld_2;
reg  vld_3;
reg  vld_4;
wire eop_1;
reg  eop_2;
reg  eop_3;
reg  eop_4;
wire [1:0] mod_1;
reg  [1:0] mod_2;
reg  [1:0] mod_3;
reg  [1:0] mod_4;
reg sop_d1;
reg vld_d1;
reg eop_d1;
reg [3:0] div_cnt_d1;
reg [31:0] dat_d1;
reg sop_d2;
reg vld_d2;
reg eop_d2;
reg [7:0] dat_d2;
/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/

/*---------------------------------------------*\
               Write to RAM FIFO
\*---------------------------------------------*/

//RAM FIFO write enable
always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		ram_wr_en <= #D 1'b0;
	else
		ram_wr_en <= #D key_dvld_drop;
end

//RAM FIFO write address
always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		ram_wr_addr <= #D 9'b0;
	else if(ram_wr_en)
		ram_wr_addr <= #D ram_wr_addr + 1;
end

//RAM FIFO write data
always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
	begin
		ram_wr_data[35] <= #D 1'b0;
		ram_wr_data[34] <= #D 1'b0;
		ram_wr_data[33:32] <= #D 2'b0;
		ram_wr_data[31:0] <= #D 32'b0;
	end
	else
	begin
		ram_wr_data[35] <= #D key_sop_drop;
		ram_wr_data[34] <= #D key_eop_drop;
		ram_wr_data[33:32] <= #D key_mod_drop;
		ram_wr_data[31:0] <= #D key_dat_drop;
	end
end 

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		in_pkt_cnt <= #D 16'b0;
	else if(conf_clr_drop)
		in_pkt_cnt <= #D 16'b0;
	else if(key_sop_drop && key_dvld_drop)
		in_pkt_cnt <= #D in_pkt_cnt + 1;
end

dpram512x36 u_ram_fifo(
    .addra (ram_wr_addr),
    .addrb (ram_rd_addr),
    .clka  (sys_clk),
    .clkb  (sys_clk),
    .dina  (ram_wr_data[35:0]), 
    .doutb (ram_rd_data[35:0]),
    .enb   (ram_rd_en), 
    .wea   (ram_wr_en)
    );
/*---------------------------------------------*\
               Read From RAM FIFO
\*---------------------------------------------*/

//Generate RAM FIFO empty signal with good timing
always @( posedge sys_clk or negedge sys_rst_n )
begin
	if( !sys_rst_n ) 
		ram_empty_cnt <= #D 10'h200;
	else if( ram_wr_en && ~(ram_rd_en && ~ram_empty) )
		ram_empty_cnt <= #D ram_empty_cnt - 1;
	else if( (ram_rd_en && ~ram_empty) && ~ram_wr_en )
		ram_empty_cnt <= #D ram_empty_cnt + 1;
end

assign  ram_empty = ram_empty_cnt[9];

//RAM read enable
assign ram_rd_en = ~lb_afull && ~ram_empty;

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		ram_rd_en_d <= #D 1'b0;
	else
		ram_rd_en_d <= #D ram_rd_en;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
	if( !sys_rst_n ) 
		ram_rd_addr <= #D 9'b0;
	else if(ram_rd_en && ~ram_empty )
		ram_rd_addr <= #D ram_rd_addr + 1;
end

//RAM FIFO pushback
always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		tmp_fifo_cnt <= #D 9'b0;
	else
		tmp_fifo_cnt <= #D ram_wr_addr - ram_rd_addr;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		drop_pb_key <= #D 1'b0;
	else if(tmp_fifo_cnt >= 9'd 490)
		drop_pb_key <= #D 1'b1;
	else if(tmp_fifo_cnt <= 9'd 465)
		drop_pb_key <= #D 1'b0;
end

//REG FIFO write enable
assign lb_wr_en = ram_rd_en_d;

lb_fifo_5cell #(36,D) u_lb_reg_fifo(
    .sys_clk     (sys_clk),
    .sys_rst_n   (sys_rst_n),
    .data_in     (ram_rd_data),
    .data_write  (lb_wr_en),
    .data_out    (lb_rd_data),
    .data_read   (lb_rd_en),
    .full_cell0  (lb_empty_n),
    .full_cell1  (),
    .full_cell2  (lb_afull),
    .full_cell3  (),
    .full_cell4  ()
    );

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		trans_flag <= #D 1'b0;
	else if(lb_rd_data[34] && !reg_fifo_two_data) //eop && !two_data
		trans_flag <= #D 1'b0;
	else if(reg_fifo_with_data)
		trans_flag <= #D 1'b1;
end

assign	lb_rd_en = trans_flag && lb_empty_n && ~afull;
/*---------------------------------------------*\
               Write to REG FIFO
\*---------------------------------------------*/

//REG FIFO write data
always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		key_wr_data <= #D 13'b0; 
	else
		key_wr_data <= #D {ci_drp_drop, ci_addr_drop, ci_dat_drop};
end

//REG FIFO write enable
always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		key_wr_en <= #D 1'b0; 
	else
		key_wr_en <= #D ci_vld_drop;
end

lb_fifo_8cell #(13,D) u_reg_fifo(
    .sys_clk     (sys_clk),
    .sys_rst_n   (sys_rst_n),
    .data_in     (key_wr_data),
    .data_write  (key_wr_en),  
    .data_out    (reg_rd_key),
    .data_read   (key_rd_en),
    .full_cell0  (reg_fifo_with_data),
    .full_cell1  (reg_fifo_two_data),
    .full_cell2  (),
    .full_cell3  (),
    .full_cell4  (reg_fifo_key_afull),
    .full_cell5  (),  
    .full_cell6  (),
    .full_cell7  ()            
    );
assign key_rd_en = lb_rd_data[34] && lb_rd_en;
//always @ (posedge sys_clk or negedge sys_rst_n)
//begin
//	if(!sys_rst_n)
//		key_rd_en <= #D 1'b0;
//	else
//		key_rd_en <= #D lb_rd_data[34] && lb_rd_en;
//end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		tmp_sop <= #D 1'b0;
	else if(lb_rd_en)
		tmp_sop <= #D lb_rd_data[35];
	else
		tmp_sop <= #D 1'b0;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		tmp_eop <= #D 1'b0;
	else if(lb_rd_en)
		tmp_eop <= #D lb_rd_data[34];
	else
		tmp_eop <= #D 1'b0;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		tmp_eop_d <= #D 1'b0;
	else
		tmp_eop_d <= #D tmp_eop;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		tmp_dvld <= #D 1'b0;
	else if(lb_rd_en)
		tmp_dvld <= #D 1'b1;
	else
		tmp_dvld <= #D 1'b0;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		tmp_mod <= #D 2'b0;
	else
		tmp_mod <= #D lb_rd_data[33:32];
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		tmp_dat <= #D 32'b0;
	else
		tmp_dat <= #D lb_rd_data[31:0];
end
reg drp_pkt_tmp;
//write data to ram
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     drp_pkt_tmp <= #D 1'b0;
  else
     drp_pkt_tmp <= #D key_rd_en && reg_rd_key[12];
    // drp_pkt <= #D 1'b0;//only for debug all packet pass
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     drp_pkt <= #D 1'b0;
  else
     drp_pkt <= #D drp_pkt_tmp;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
     wen <= #D 1'b0;
  else
     wen <= #D tmp_dvld;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin