cam_if.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        tmp_hit <= #D 1'b0;
    else
        tmp_hit <= #D cam_match_ci;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        tmp_addr <= #D 8'b0;
    else
        tmp_addr <= #D cam_match_addr_ci;
end

//write data into cam
//first give data(1-9), then give the address(0)
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       ci_wr_addr_cam <= #D 8'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd0)
       ci_wr_addr_cam <= #D conf_wdat_ci[7:0];
end

//always @(posedge sys_clk or negedge sys_rst_n)
//begin
//  if(!sys_rst_n) 
//       ci_din_cam[143:128] <= #D 16'b0;
//  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd1)
//       ci_din_cam[143:128] <= #D conf_wdat_ci;
//end
//
//always @(posedge sys_clk or negedge sys_rst_n)
//begin
//  if(!sys_rst_n) 
//       ci_din_cam[127:112] <= #D 16'b0;
//  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd2)
//       ci_din_cam[127:112] <= #D conf_wdat_ci;
//end
//
//always @(posedge sys_clk or negedge sys_rst_n)
//begin
//  if(!sys_rst_n) 
//       ci_din_cam[111:96] <= #D 16'b0;
//  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd3)
//       ci_din_cam[111:96] <= #D conf_wdat_ci;
//end
//
//always @(posedge sys_clk or negedge sys_rst_n)
//begin
//  if(!sys_rst_n) 
//       ci_din_cam[95:80] <= #D 16'b0;
//  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd1)
//       ci_din_cam[95:80] <= #D conf_wdat_ci;
//end
//
//always @(posedge sys_clk or negedge sys_rst_n)
//begin
//  if(!sys_rst_n) 
//       ci_din_cam[79:64] <= #D 16'b0;
//  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd2)
//       ci_din_cam[79:64] <= #D conf_wdat_ci;
//end
//
//always @(posedge sys_clk or negedge sys_rst_n)
//begin
//  if(!sys_rst_n) 
//       ci_din_cam[63:48] <= #D 16'b0;
//  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd3)
//       ci_din_cam[63:48] <= #D conf_wdat_ci;
//end
//
//always @(posedge sys_clk or negedge sys_rst_n)
//begin
//  if(!sys_rst_n) 
//       ci_din_cam[47:32] <= #D 16'b0;
//  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd4)
//       ci_din_cam[47:32] <= #D conf_wdat_ci;
//end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       ci_din_cam[31:16] <= #D 16'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd1)
       ci_din_cam[31:16] <= #D conf_wdat_ci;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       ci_din_cam[15:0] <= #D 16'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd2)
       ci_din_cam[15:0] <= #D conf_wdat_ci;
end

//write enable signal
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n)
       ci_we_cam <= #D 1'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd0)
       ci_we_cam <= #D 1'b1;
  else
  	   ci_we_cam <= #D 1'b0;
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       ci_cmp_dmsk_cam[31:0] <= #D 32'hffff;
  else if(sip_mtch_en || dip_mtch_en)
       ci_cmp_dmsk_cam[31:0] <= #D 32'h0;
  else if(sp_mtch_en)
       ci_cmp_dmsk_cam[31:0] <= #D 32'h00ff;
  else if(dp_mtch_en)
       ci_cmp_dmsk_cam[31:0] <= #D 32'hff00;
  else
       ci_cmp_dmsk_cam[31:0] <= #D 32'hffff;
end
//-------------------------------------------//

//write data to result ram
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       rst_addra <= #D 8'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd10)
       rst_addra <= #D conf_wdat_ci[7:0];
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       rst_dina <= #D 5'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd10)
       rst_dina <= #D conf_wdat_ci[12:8];
end

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       rst_wea <= #D 1'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd10)
       rst_wea <= #D conf_wdat_ci[15];
  else
       rst_wea <= #D 1'b0;
end

dpram256x5 u_rst_table(
    .addra (rst_addra[7:0]),
    .addrb (rst_addrb[7:0]),
    .clka  (sys_clk),
    .clkb  (sys_clk),
    .dina  (rst_dina),
    .dinb  (5'b0),
    .douta (rst_douta_ram),
    .doutb (rst_doutb_ram),
    .ena   (rst_ena),
    .enb   (rst_enb),
    .wea   (rst_wea),
    .web   (1'b0)
    );

always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       rst_ena <= #D 1'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd10)
       rst_ena <= #D 1'b1;
  else
       rst_ena <= #D 1'b0;
end

//read result table data
always @ (posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
        rst_enb <= #D 1'b0;
    else
        rst_enb <= #D tmp_hit;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n )
        rst_addrb <= #D 8'b0;
    else
        rst_addrb <= #D tmp_addr;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
	      rst_doutb <= #D 5'b0;
    else
        rst_doutb <= #D rst_doutb_ram;
end

always @ (posedge sys_clk or negedge sys_rst_n)
begin
    if(!sys_rst_n)
	      rst_douta <= #D 5'b0;
    else
        rst_douta <= #D rst_douta_ram;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
    begin
        f1_vld <= #D 1'b0;
        f1_hit <= #D 1'b0;
        f1_adr <= #D 8'b0;
        f2_vld <= #D 1'b0;
        f2_hit <= #D 1'b0;
        f2_adr <= #D 8'b0;
        f3_vld <= #D 1'b0;
        f3_hit <= #D 1'b0;
        f3_adr <= #D 8'b0;
    end    
    else
    begin
        f1_vld <= #D tmp_vld;
        f1_hit <= #D tmp_hit;
        f1_adr <= #D tmp_addr;
        f2_vld <= #D f1_vld;
        f2_hit <= #D f1_hit;
        f2_adr <= #D f1_adr;
        f3_vld <= #D f2_vld;
        f3_hit <= #D f2_hit;
        f3_adr <= #D f2_adr;
    end
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        ci_vld_drop <= #D 1'b0;
    else
        ci_vld_drop <= #D f3_vld;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        ci_drp_drop <= #D 1'b1;
    else if(f3_hit && rst_doutb[4])//drop directly
        ci_drp_drop <= #D 1'b1;
    else if(f3_hit && rst_doutb[3])//if not drop then sample
        ci_drp_drop <= #D sample_rst;
    else
        ci_drp_drop <= #D 1'b0;//f3_vld;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        ci_addr_drop <= #D 8'b0;
    else
        ci_addr_drop <= #D f3_adr;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        ci_dat_drop <= #D 4'b0;
    else
        ci_dat_drop <= #D rst_doutb[3:0];
end

//sip match enable
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       sip_mtch_en <= #D 1'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd11)
       sip_mtch_en <= #D conf_wdat_ci[3];
end

//dip match enable
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       dip_mtch_en <= #D 1'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd11)
       dip_mtch_en <= #D conf_wdat_ci[2];
end

//sp match enable
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       sp_mtch_en <= #D 1'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd11)
       sp_mtch_en <= #D conf_wdat_ci[1];
end

//dp match enable
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n) 
       dp_mtch_en <= #D 1'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd11)
       dp_mtch_en <= #D conf_wdat_ci[0];
end

//Read data to conf                       
always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        ci_rdat_conf <= #D 16'h0;
    else if( conf_rd_ci )
    begin
        case( conf_addr_ci[3:0] )
        4'd0:  ci_rdat_conf <= #D {8'b0,ci_wr_addr_cam};
        4'd1:  ci_rdat_conf <= #D ci_din_cam[31:16];
        4'd2:  ci_rdat_conf <= #D ci_din_cam[15:0];
        4'd10: ci_rdat_conf <= #D {rst_wea,2'b0,rst_douta,rst_addra};
        4'd11: ci_rdat_conf <= #D {12'b0,sip_mtch_en,dip_mtch_en,sp_mtch_en,dp_mtch_en};
        4'd12: ci_rdat_conf <= #D sample_dat;
        default : ci_rdat_conf <= #D 16'h0;
        endcase
    end
end

endmodule