cam_if.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

//generate search key,and search the cam
//-----------------------------------------------------------------------------
// Title      : 
// Project    : 
//-----------------------------------------------------------------------------
// File       : cam_if.v
// Author     : 
// Date       : 07-11-1
//-----------------------------------------------------------------------------
// Description: 
//
//-----------------------------------------------------------------------------

`timescale 1ns/10ps

module cam_if(
sys_clk,
sys_rst_n,
key_sok_ci,
key_eok_ci,
key_key_ci,
key_kvld_ci,
ci_din_cam,
ci_cmp_dmsk_cam,
ci_cmp_din_cam,
ci_en_cam,
ci_we_cam,
ci_wr_addr_cam,
cam_busy_ci,
cam_match_ci,
cam_match_addr_ci,
ci_vld_drop,
ci_drp_drop, 
ci_addr_drop,
ci_dat_drop,
conf_wr_ci,
conf_rd_ci,
conf_clr_ci,
conf_wdat_ci,
conf_addr_ci,
ci_rdat_conf
);

/*-------------------------------------------------------------------*\
                          Parameter Description
\*-------------------------------------------------------------------*/

parameter D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

//global signal
input                sys_clk;
input                sys_rst_n;

//interface with pre
input               key_sok_ci;
input               key_eok_ci;
input   [31:0]      key_key_ci;
input               key_kvld_ci;

//interface with cam
output   [31 : 0]    ci_din_cam;
output   [31 : 0]    ci_cmp_dmsk_cam;
output   [31 : 0]    ci_cmp_din_cam;
output               ci_en_cam;
output               ci_we_cam;
output   [7 : 0]     ci_wr_addr_cam;
input                cam_busy_ci;
input                cam_match_ci;
input    [7 : 0]     cam_match_addr_ci;

//interface with drop
output               ci_vld_drop;
output               ci_drp_drop;
output   [7:0]       ci_addr_drop;
output   [3:0]       ci_dat_drop;

//interface with conf
input                conf_wr_ci;
input                conf_rd_ci;
input                conf_clr_ci;
input    [15:0]      conf_wdat_ci;
input    [3:0]       conf_addr_ci;
output   [15:0]      ci_rdat_conf;
/*-------------------------------------------------------------------*\
                          Reg/Wire Description
\*-------------------------------------------------------------------*/
reg            frame_2nd;
reg            frame_3rd;
reg            frame_4th;
reg   [143:0]  cmp_dat;
reg            eok_d;
reg            eok_d1;
reg            eok_d2;
reg   [31:0]   ci_cmp_din_cam;
reg            ci_en_cam;
reg            tmp_vld;
reg            tmp_hit;
reg   [7:0]    tmp_addr;
reg   [7:0]    ci_wr_addr_cam;
reg   [31:0]   ci_din_cam;
reg            ci_we_cam;
reg   [7:0]    rst_addra;
reg   [4:0]    rst_dina;
reg            rst_wea;
wire  [4:0]    rst_doutb_ram;
wire  [4:0]    rst_douta_ram;
reg            rst_ena;
reg            rst_enb;
reg   [7:0]    rst_addrb;
reg   [4:0]    rst_doutb;
reg   [4:0]    rst_douta;
reg            f1_vld;
reg            f1_hit;
reg   [7:0]    f1_adr;
reg            f2_vld;
reg            f2_hit;
reg   [7:0]    f2_adr;
reg            f3_vld;
reg            f3_hit;
reg   [7:0]    f3_adr;
reg            ci_vld_drop;
reg            ci_drp_drop;
reg   [7:0]    ci_addr_drop;
reg   [3:0]    ci_dat_drop;
reg   [15:0]   ci_rdat_conf;
reg   [31:0]   ci_cmp_dmsk_cam;
reg            sip_mtch_en;
reg            dip_mtch_en;
reg            sp_mtch_en;
reg            dp_mtch_en;
reg   [15:0]   sp;
reg   [15:0]   dp;
reg   [15:0]   sample_dat;
reg   [7:0]    sample_addr_tmp;
reg   [3:0]    sample_addr;
reg            sample_rst;
/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/

//compare
always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        frame_2nd <= #D 1'b0;
    else if( key_sok_ci && key_kvld_ci )
        frame_2nd <= #D 1'b1;
    else if( key_kvld_ci )
        frame_2nd <= #D 1'b0;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        frame_3rd <= #D 1'b0;
    else if( frame_2nd && key_kvld_ci )
        frame_3rd <= #D 1'b1;
    else if( key_kvld_ci )
        frame_3rd <= #D 1'b0;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        frame_4th <= #D 1'b0;
    else if( frame_3rd && key_kvld_ci )
        frame_4th <= #D 1'b1;
    else if( key_kvld_ci )
        frame_4th <= #D 1'b0;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        cmp_dat[143:112] <= #D 32'h0;
    else if( key_sok_ci && key_kvld_ci )
        cmp_dat[143:112] <= #D key_key_ci[31:0];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        cmp_dat[111:80] <= #D 32'h0;
    else if( frame_2nd && key_kvld_ci )
        cmp_dat[111:80] <= #D key_key_ci[31:0];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        cmp_dat[79:48] <= #D 32'h0;
    else if( frame_3rd && key_kvld_ci )
        cmp_dat[79:48] <= #D key_key_ci[31:0];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        cmp_dat[47:16] <= #D 32'h0;
    else if( frame_4th && key_kvld_ci )
        cmp_dat[47:16] <= #D key_key_ci[31:0];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        cmp_dat[15:0] <= #D 16'h0;
    else if( key_eok_ci && key_kvld_ci )
        cmp_dat[15:0] <= #D key_key_ci[31:16];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        sp <= #D 16'h0;
    else if( frame_4th && key_kvld_ci )
        sp <= #D key_key_ci[31:16];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        dp <= #D 16'h0;
    else if( frame_4th && key_kvld_ci )
        dp <= #D key_key_ci[15:0];
end
//sample data
always @(posedge sys_clk or negedge sys_rst_n)
begin
  if(!sys_rst_n)
       sample_dat <= #D 16'b0;
  else if(conf_wr_ci && conf_addr_ci[3:0] == 4'd12)
       sample_dat <= #D conf_wdat_ci[15:0];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        sample_addr_tmp <= #D 8'h0;
    else
        sample_addr_tmp <= #D sp[7:0] ^ sp[15:8] ^ dp[7:0] ^ dp [15:8];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        sample_addr <= #D 4'h0;
    else
        sample_addr <= #D sample_addr_tmp[7:4] ^ sample_addr_tmp[3:0];
end

always @( posedge sys_clk or negedge sys_rst_n)
begin
    if( !sys_rst_n )
        sample_rst <= #D 1'b0;
    else
    begin
        case( sample_addr[3:0] )
        4'h0:  sample_rst <= #D sample_dat[0];
        4'h1:  sample_rst <= #D sample_dat[1];
        4'h2:  sample_rst <= #D sample_dat[2];
        4'h3:  sample_rst <= #D sample_dat[3];
        4'h4:  sample_rst <= #D sample_dat[4];
        4'h5:  sample_rst <= #D sample_dat[5];
        4'h6:  sample_rst <= #D sample_dat[6];
        4'h7:  sample_rst <= #D sample_dat[7];
        4'h8:  sample_rst <= #D sample_dat[8];
        4'h9:  sample_rst <= #D sample_dat[9];
        4'ha:  sample_rst <= #D sample_dat[10];
        4'hb:  sample_rst <= #D sample_dat[11];
        4'hc:  sample_rst <= #D sample_dat[12];
        4'hd:  sample_rst <= #D sample_dat[13];
        4'he:  sample_rst <= #D sample_dat[14];
        4'hf:  sample_rst <= #D sample_dat[15];
        endcase
    end
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
    begin
        eok_d <= #D 1'b0;
        eok_d1<= #D 1'b0;
        eok_d2<= #D 1'b0;
    end
    else
    begin
        eok_d <= #D key_eok_ci && key_kvld_ci;
        eok_d1<= #D eok_d;
        eok_d2<= #D eok_d1;
    end
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n )
        ci_cmp_din_cam <= #D 32'h0;
    else if(eok_d && sip_mtch_en)
        ci_cmp_din_cam <= #D cmp_dat[111:80];
    else if(eok_d && dip_mtch_en)
        ci_cmp_din_cam <= #D cmp_dat[79:48];
    else if(eok_d && sp_mtch_en)
        ci_cmp_din_cam <= #D {cmp_dat[47:32],16'b0};
    else if(eok_d && dp_mtch_en)
        ci_cmp_din_cam <= #D {16'b0,cmp_dat[31:16]};
    else
        ci_cmp_din_cam <= #D cmp_dat[111:80];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n )
        ci_en_cam <= #D 1'h1;
    else
        ci_en_cam <= #D 1'b1;
end

//send result to drop
always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        tmp_vld <= #D 1'b0;
    else
        tmp_vld <= #D eok_d2;
end