myfirewall_0_wrapper.vhd

本系统由服务器软件控制平台和fpga硬件处理系统组成

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-- myfirewall_0_wrapper.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library myfirewall_v1_00_a;
use myfirewall_v1_00_a.All;

entity myfirewall_0_wrapper is
  port (
    sys_clk_in_100m : in std_logic;
    sys_rst_in : in std_logic;
    ppc_ce_n_conf : out std_logic;
    ppc_we_n_conf : out std_logic;
    ppc_re_n_conf : out std_logic;
    ppc_clr_n_conf : out std_logic;
    ppc_addr_conf : out std_logic_vector(0 to 7);
    ppc_wdat_conf : out std_logic_vector(0 to 15);
    conf_rdat_ppc : in std_logic_vector(0 to 15);
    OPB_Clk : in std_logic;
    OPB_Rst : in std_logic;
    Sl_DBus : out std_logic_vector(0 to 31);
    Sl_errAck : out std_logic;
    Sl_retry : out std_logic;
    Sl_toutSup : out std_logic;
    Sl_xferAck : out std_logic;
    OPB_ABus : in std_logic_vector(0 to 31);
    OPB_BE : in std_logic_vector(0 to 3);
    OPB_DBus : in std_logic_vector(0 to 31);
    OPB_RNW : in std_logic;
    OPB_select : in std_logic;
    OPB_seqAddr : in std_logic
  );
  attribute x_core_info : STRING;
  attribute x_core_info of myfirewall_0_wrapper: entity is "myfirewall_v1_00_a";

end myfirewall_0_wrapper;

architecture STRUCTURE of myfirewall_0_wrapper is

  component myfirewall is
    generic (
      C_BASEADDR : std_logic_vector;
      C_HIGHADDR : std_logic_vector;
      C_OPB_AWIDTH : INTEGER;
      C_OPB_DWIDTH : INTEGER;
      C_FAMILY : STRING
    );
    port (
      sys_clk_in_100m : in std_logic;
      sys_rst_in : in std_logic;
      ppc_ce_n_conf : out std_logic;
      ppc_we_n_conf : out std_logic;
      ppc_re_n_conf : out std_logic;
      ppc_clr_n_conf : out std_logic;
      ppc_addr_conf : out std_logic_vector(0 to 7);
      ppc_wdat_conf : out std_logic_vector(0 to 15);
      conf_rdat_ppc : in std_logic_vector(0 to 15);
      OPB_Clk : in std_logic;
      OPB_Rst : in std_logic;
      Sl_DBus : out std_logic_vector(0 to (C_OPB_DWIDTH-1));
      Sl_errAck : out std_logic;
      Sl_retry : out std_logic;
      Sl_toutSup : out std_logic;
      Sl_xferAck : out std_logic;
      OPB_ABus : in std_logic_vector(0 to (C_OPB_AWIDTH-1));
      OPB_BE : in std_logic_vector(0 to ((C_OPB_DWIDTH/8)-1));
      OPB_DBus : in std_logic_vector(0 to (C_OPB_DWIDTH-1));
      OPB_RNW : in std_logic;
      OPB_select : in std_logic;
      OPB_seqAddr : in std_logic
    );
  end component;

begin

  myfirewall_0 : myfirewall
    generic map (
      C_BASEADDR => X"40700000",
      C_HIGHADDR => X"4070FFFF",
      C_OPB_AWIDTH => 32,
      C_OPB_DWIDTH => 32,
      C_FAMILY => "virtex2p"
    )
    port map (
      sys_clk_in_100m => sys_clk_in_100m,
      sys_rst_in => sys_rst_in,
      ppc_ce_n_conf => ppc_ce_n_conf,
      ppc_we_n_conf => ppc_we_n_conf,
      ppc_re_n_conf => ppc_re_n_conf,
      ppc_clr_n_conf => ppc_clr_n_conf,
      ppc_addr_conf => ppc_addr_conf,
      ppc_wdat_conf => ppc_wdat_conf,
      conf_rdat_ppc => conf_rdat_ppc,
      OPB_Clk => OPB_Clk,
      OPB_Rst => OPB_Rst,
      Sl_DBus => Sl_DBus,
      Sl_errAck => Sl_errAck,
      Sl_retry => Sl_retry,
      Sl_toutSup => Sl_toutSup,
      Sl_xferAck => Sl_xferAck,
      OPB_ABus => OPB_ABus,
      OPB_BE => OPB_BE,
      OPB_DBus => OPB_DBus,
      OPB_RNW => OPB_RNW,
      OPB_select => OPB_select,
      OPB_seqAddr => OPB_seqAddr
    );

end architecture STRUCTURE;