system.vhd

本系统由服务器软件控制平台和fpga硬件处理系统组成

      OPB_seqAddr => opb_OPB_seqAddr,
      Sln_DBus => opb_Sl_DBus(32 to 63),
      Sln_errAck => opb_Sl_errAck(1),
      Sln_retry => opb_Sl_retry(1),
      Sln_toutSup => opb_Sl_toutSup(1),
      Sln_xferAck => opb_Sl_xferAck(1),
      IP2INTC_Irpt => open,
      GPIO_in => net_gnd4,
      GPIO_d_out => open,
      GPIO_t_out => open,
      GPIO2_in => net_gnd4,
      GPIO2_d_out => open,
      GPIO2_t_out => open,
      GPIO_IO_I => fpga_0_LEDs_4Bit_GPIO_IO_I,
      GPIO_IO_O => fpga_0_LEDs_4Bit_GPIO_IO_O,
      GPIO_IO_T => fpga_0_LEDs_4Bit_GPIO_IO_T,
      GPIO2_IO_I => net_gnd4,
      GPIO2_IO_O => open,
      GPIO2_IO_T => open
    );

  dipsws_4bit : dipsws_4bit_wrapper
    port map (
      OPB_ABus => opb_OPB_ABus,
      OPB_BE => opb_OPB_BE,
      OPB_Clk => sys_clk_s,
      OPB_DBus => opb_OPB_DBus,
      OPB_RNW => opb_OPB_RNW,
      OPB_Rst => opb_OPB_Rst,
      OPB_select => opb_OPB_select,
      OPB_seqAddr => opb_OPB_seqAddr,
      Sln_DBus => opb_Sl_DBus(64 to 95),
      Sln_errAck => opb_Sl_errAck(2),
      Sln_retry => opb_Sl_retry(2),
      Sln_toutSup => opb_Sl_toutSup(2),
      Sln_xferAck => opb_Sl_xferAck(2),
      IP2INTC_Irpt => open,
      GPIO_in => net_gnd4,
      GPIO_d_out => open,
      GPIO_t_out => open,
      GPIO2_in => net_gnd4,
      GPIO2_d_out => open,
      GPIO2_t_out => open,
      GPIO_IO_I => fpga_0_DIPSWs_4Bit_GPIO_IO_I,
      GPIO_IO_O => fpga_0_DIPSWs_4Bit_GPIO_IO_O,
      GPIO_IO_T => fpga_0_DIPSWs_4Bit_GPIO_IO_T,
      GPIO2_IO_I => net_gnd4,
      GPIO2_IO_O => open,
      GPIO2_IO_T => open
    );

  pushbuttons_5bit : pushbuttons_5bit_wrapper
    port map (
      OPB_ABus => opb_OPB_ABus,
      OPB_BE => opb_OPB_BE,
      OPB_Clk => sys_clk_s,
      OPB_DBus => opb_OPB_DBus,
      OPB_RNW => opb_OPB_RNW,
      OPB_Rst => opb_OPB_Rst,
      OPB_select => opb_OPB_select,
      OPB_seqAddr => opb_OPB_seqAddr,
      Sln_DBus => opb_Sl_DBus(96 to 127),
      Sln_errAck => opb_Sl_errAck(3),
      Sln_retry => opb_Sl_retry(3),
      Sln_toutSup => opb_Sl_toutSup(3),
      Sln_xferAck => opb_Sl_xferAck(3),
      IP2INTC_Irpt => open,
      GPIO_in => net_gnd5,
      GPIO_d_out => open,
      GPIO_t_out => open,
      GPIO2_in => net_gnd5,
      GPIO2_d_out => open,
      GPIO2_t_out => open,
      GPIO_IO_I => fpga_0_PushButtons_5Bit_GPIO_IO_I,
      GPIO_IO_O => fpga_0_PushButtons_5Bit_GPIO_IO_O,
      GPIO_IO_T => fpga_0_PushButtons_5Bit_GPIO_IO_T,
      GPIO2_IO_I => net_gnd5,
      GPIO2_IO_O => open,
      GPIO2_IO_T => open
    );

  ps2_ports : ps2_ports_wrapper
    port map (
      OPB_BE => opb_OPB_BE,
      IPIF_Rst => opb_OPB_Rst,
      OPB_Select => opb_OPB_select,
      OPB_DBus => opb_OPB_DBus,
      OPB_Clk => sys_clk_s,
      OPB_ABus => opb_OPB_ABus,
      OPB_RNW => opb_OPB_RNW,
      OPB_seqAddr => opb_OPB_seqAddr,
      Sys_Intr1 => open,
      Sys_Intr2 => open,
      Sln_XferAck => opb_Sl_xferAck(4),
      Sln_DBus => opb_Sl_DBus(128 to 159),
      Sln_DBusEn => open,
      Sln_errAck => opb_Sl_errAck(4),
      Sln_retry => opb_Sl_retry(4),
      Sln_toutSup => opb_Sl_toutSup(4),
      Clkin1 => PS2_Ports_Clkin1_PS2_Ports_IO_ADAPTER_ps2_clk_rx_1,
      Clkpd1 => PS2_Ports_Clkpd1_PS2_Ports_IO_ADAPTER_ps2_clk_tx_1,
      Rx1 => PS2_Ports_IO_ADAPTER_ps2_d_rx_1_PS2_Ports_Rx1,
      Txpd1 => PS2_Ports_IO_ADAPTER_ps2_d_tx_1_PS2_Ports_Txpd1,
      Clkin2 => PS2_Ports_Clkin2_PS2_Ports_IO_ADAPTER_ps2_clk_rx_2,
      Clkpd2 => PS2_Ports_Clkpd2_PS2_Ports_IO_ADAPTER_ps2_clk_tx_2,
      Rx2 => PS2_Ports_IO_ADAPTER_ps2_d_rx_2_PS2_Ports_Rx2,
      Txpd2 => PS2_Ports_IO_ADAPTER_ps2_d_tx_2_PS2_Ports_Txpd2
    );

  plb_bram_if_cntlr_1 : plb_bram_if_cntlr_1_wrapper
    port map (
      plb_clk => sys_clk_s,
      plb_rst => plb_PLB_Rst,
      plb_abort => plb_PLB_abort,
      plb_abus => plb_PLB_ABus,
      plb_be => plb_PLB_BE,
      plb_buslock => plb_PLB_busLock,
      plb_compress => plb_PLB_compress,
      plb_guarded => plb_PLB_guarded,
      plb_lockerr => plb_PLB_lockErr,
      plb_masterid => plb_PLB_masterID(0 to 0),
      plb_msize => plb_PLB_MSize,
      plb_ordered => plb_PLB_ordered,
      plb_pavalid => plb_PLB_PAValid,
      plb_rnw => plb_PLB_RNW,
      plb_size => plb_PLB_size,
      plb_type => plb_PLB_type,
      sl_addrack => plb_Sl_addrAck(1),
      sl_mbusy => plb_Sl_MBusy(2 to 3),
      sl_merr => plb_Sl_MErr(2 to 3),
      sl_rearbitrate => plb_Sl_rearbitrate(1),
      sl_ssize => plb_Sl_SSize(2 to 3),
      sl_wait => plb_Sl_wait(1),
      plb_rdprim => plb_PLB_rdPrim,
      plb_savalid => plb_PLB_SAValid,
      plb_wrprim => plb_PLB_wrPrim,
      plb_wrburst => plb_PLB_wrBurst,
      plb_wrdbus => plb_PLB_wrDBus,
      sl_wrbterm => plb_Sl_wrBTerm(1),
      sl_wrcomp => plb_Sl_wrComp(1),
      sl_wrdack => plb_Sl_wrDAck(1),
      plb_rdburst => plb_PLB_rdBurst,
      sl_rdbterm => plb_Sl_rdBTerm(1),
      sl_rdcomp => plb_Sl_rdComp(1),
      sl_rddack => plb_Sl_rdDAck(1),
      sl_rddbus => plb_Sl_rdDBus(64 to 127),
      sl_rdwdaddr => plb_Sl_rdWdAddr(4 to 7),
      plb_pendreq => plb_PLB_pendReq,
      plb_pendpri => plb_PLB_pendPri,
      plb_reqpri => plb_PLB_reqPri,
      bram_rst => plb_bram_if_cntlr_1_port_BRAM_Rst,
      bram_clk => plb_bram_if_cntlr_1_port_BRAM_Clk,
      bram_en => plb_bram_if_cntlr_1_port_BRAM_EN,
      bram_wen => plb_bram_if_cntlr_1_port_BRAM_WEN,
      bram_addr => plb_bram_if_cntlr_1_port_BRAM_Addr,
      bram_din => plb_bram_if_cntlr_1_port_BRAM_Din,
      bram_dout => plb_bram_if_cntlr_1_port_BRAM_Dout
    );

  plb_bram_if_cntlr_1_bram : plb_bram_if_cntlr_1_bram_wrapper
    port map (
      BRAM_Rst_A => plb_bram_if_cntlr_1_port_BRAM_Rst,
      BRAM_Clk_A => plb_bram_if_cntlr_1_port_BRAM_Clk,
      BRAM_EN_A => plb_bram_if_cntlr_1_port_BRAM_EN,
      BRAM_WEN_A => plb_bram_if_cntlr_1_port_BRAM_WEN,
      BRAM_Addr_A => plb_bram_if_cntlr_1_port_BRAM_Addr,
      BRAM_Din_A => plb_bram_if_cntlr_1_port_BRAM_Din,
      BRAM_Dout_A => plb_bram_if_cntlr_1_port_BRAM_Dout,
      BRAM_Rst_B => net_gnd0,
      BRAM_Clk_B => net_gnd0,
      BRAM_EN_B => net_gnd0,
      BRAM_WEN_B => net_gnd8,
      BRAM_Addr_B => net_gnd32,
      BRAM_Din_B => open,
      BRAM_Dout_B => net_gnd64
    );

  ps2_ports_io_adapter : ps2_ports_io_adapter_wrapper
    port map (
      ps2_clk_tx_1 => PS2_Ports_Clkpd1_PS2_Ports_IO_ADAPTER_ps2_clk_tx_1,
      ps2_clk_rx_1 => PS2_Ports_Clkin1_PS2_Ports_IO_ADAPTER_ps2_clk_rx_1,
      ps2_d_tx_1 => PS2_Ports_IO_ADAPTER_ps2_d_tx_1_PS2_Ports_Txpd1,
      ps2_d_rx_1 => PS2_Ports_IO_ADAPTER_ps2_d_rx_1_PS2_Ports_Rx1,
      ps2_clk_tx_2 => PS2_Ports_Clkpd2_PS2_Ports_IO_ADAPTER_ps2_clk_tx_2,
      ps2_clk_rx_2 => PS2_Ports_Clkin2_PS2_Ports_IO_ADAPTER_ps2_clk_rx_2,
      ps2_d_tx_2 => PS2_Ports_IO_ADAPTER_ps2_d_tx_2_PS2_Ports_Txpd2,
      ps2_d_rx_2 => PS2_Ports_IO_ADAPTER_ps2_d_rx_2_PS2_Ports_Rx2,
      ps2_mouse_clk_I => fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_I,
      ps2_mouse_clk_O => fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_O,
      ps2_mouse_clk_T => fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_T,
      ps2_mouse_data_I => fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_I,
      ps2_mouse_data_O => fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_O,
      ps2_mouse_data_T => fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_T,
      ps2_keyb_clk_I => fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_I,
      ps2_keyb_clk_O => fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_O,
      ps2_keyb_clk_T => fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_T,
      ps2_keyb_data_I => fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_I,
      ps2_keyb_data_O => fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_O,
      ps2_keyb_data_T => fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_T
    );

  dcm_0 : dcm_0_wrapper
    port map (
      RST => net_gnd0,
      CLKIN => dcm_clk_s,
      CLKFB => sys_clk_s,
      PSEN => net_gnd0,
      PSINCDEC => net_gnd0,
      PSCLK => net_gnd0,
      DSSEN => net_gnd0,
      CLK0 => sys_clk_s,
      CLK90 => open,
      CLK180 => open,
      CLK270 => open,
      CLKDV => open,
      CLK2X => open,
      CLK2X180 => open,
      CLKFX => open,
      CLKFX180 => open,
      STATUS => open,
      LOCKED => dcm_0_lock,
      PSDONE => open
    );

  myfirewall_0 : myfirewall_0_wrapper
    port map (
      sys_clk_in_100m => sys_clk_s,
      sys_rst_in => sys_rst_s,
      ppc_ce_n_conf => myfirewall_0_ppc_ce_n_conf,
      ppc_we_n_conf => myfirewall_0_ppc_we_n_conf,
      ppc_re_n_conf => myfirewall_0_ppc_re_n_conf,
      ppc_clr_n_conf => myfirewall_0_ppc_clr_n_conf,
      ppc_addr_conf => myfirewall_0_ppc_addr_conf,
      ppc_wdat_conf => myfirewall_0_ppc_wdat_conf,
      conf_rdat_ppc => myfirewall_0_conf_rdat_ppc,
      OPB_Clk => sys_clk_s,
      OPB_Rst => opb_OPB_Rst,
      Sl_DBus => opb_Sl_DBus(160 to 191),
      Sl_errAck => opb_Sl_errAck(5),
      Sl_retry => opb_Sl_retry(5),
      Sl_toutSup => opb_Sl_toutSup(5),
      Sl_xferAck => opb_Sl_xferAck(5),
      OPB_ABus => opb_OPB_ABus,
      OPB_BE => opb_OPB_BE,
      OPB_DBus => opb_OPB_DBus,
      OPB_RNW => opb_OPB_RNW,
      OPB_select => opb_OPB_select,
      OPB_seqAddr => opb_OPB_seqAddr
    );

  iobuf_0 : IOBUF
    port map (
      I => fpga_0_LEDs_4Bit_GPIO_IO_O(0),
      IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(0),
      O => fpga_0_LEDs_4Bit_GPIO_IO_I(0),
      T => fpga_0_LEDs_4Bit_GPIO_IO_T(0)
    );

  iobuf_1 : IOBUF
    port map (
      I => fpga_0_LEDs_4Bit_GPIO_IO_O(1),
      IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(1),
      O => fpga_0_LEDs_4Bit_GPIO_IO_I(1),
      T => fpga_0_LEDs_4Bit_GPIO_IO_T(1)
    );

  iobuf_2 : IOBUF
    port map (
      I => fpga_0_LEDs_4Bit_GPIO_IO_O(2),
      IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(2),
      O => fpga_0_LEDs_4Bit_GPIO_IO_I(2),
      T => fpga_0_LEDs_4Bit_GPIO_IO_T(2)
    );

  iobuf_3 : IOBUF
    port map (
      I => fpga_0_LEDs_4Bit_GPIO_IO_O(3),
      IO => fpga_0_LEDs_4Bit_GPIO_IO_pin(3),
      O => fpga_0_LEDs_4Bit_GPIO_IO_I(3),
      T => fpga_0_LEDs_4Bit_GPIO_IO_T(3)
    );

  iobuf_4 : IOBUF
    port map (
      I => fpga_0_DIPSWs_4Bit_GPIO_IO_O(0),
      IO => fpga_0_DIPSWs_4Bit_GPIO_IO_pin(0),
      O => fpga_0_DIPSWs_4Bit_GPIO_IO_I(0),
      T => fpga_0_DIPSWs_4Bit_GPIO_IO_T(0)
    );

  iobuf_5 : IOBUF
    port map (
      I => fpga_0_DIPSWs_4Bit_GPIO_IO_O(1),
      IO => fpga_0_DIPSWs_4Bit_GPIO_IO_pin(1),
      O => fpga_0_DIPSWs_4Bit_GPIO_IO_I(1),
      T => fpga_0_DIPSWs_4Bit_GPIO_IO_T(1)
    );

  iobuf_6 : IOBUF
    port map (
      I => fpga_0_DIPSWs_4Bit_GPIO_IO_O(2),
      IO => fpga_0_DIPSWs_4Bit_GPIO_IO_pin(2),
      O => fpga_0_DIPSWs_4Bit_GPIO_IO_I(2),
      T => fpga_0_DIPSWs_4Bit_GPIO_IO_T(2)
    );

  iobuf_7 : IOBUF
    port map (
      I => fpga_0_DIPSWs_4Bit_GPIO_IO_O(3),
      IO => fpga_0_DIPSWs_4Bit_GPIO_IO_pin(3),
      O => fpga_0_DIPSWs_4Bit_GPIO_IO_I(3),
      T => fpga_0_DIPSWs_4Bit_GPIO_IO_T(3)
    );

  iobuf_8 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(0),
      IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(0),
      O => fpga_0_PushButtons_5Bit_GPIO_IO_I(0),
      T => fpga_0_PushButtons_5Bit_GPIO_IO_T(0)
    );

  iobuf_9 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(1),
      IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(1),
      O => fpga_0_PushButtons_5Bit_GPIO_IO_I(1),
      T => fpga_0_PushButtons_5Bit_GPIO_IO_T(1)
    );

  iobuf_10 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(2),
      IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(2),
      O => fpga_0_PushButtons_5Bit_GPIO_IO_I(2),
      T => fpga_0_PushButtons_5Bit_GPIO_IO_T(2)
    );

  iobuf_11 : IOBUF
    port map (
      I => fpga_0_PushButtons_5Bit_GPIO_IO_O(3),