system_stub.vhd

本系统由服务器软件控制平台和fpga硬件处理系统组成

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-- system_stub.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_stub is
  port (
    fpga_0_RS232_Uart_1_RX_pin : in std_logic;
    fpga_0_RS232_Uart_1_TX_pin : out std_logic;
    fpga_0_LEDs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
    fpga_0_DIPSWs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
    fpga_0_PushButtons_5Bit_GPIO_IO_pin : inout std_logic_vector(0 to 4);
    fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin : inout std_logic;
    fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin : inout std_logic;
    fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin : inout std_logic;
    fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin : inout std_logic;
    fpga_0_net_gnd_pin : out std_logic;
    fpga_0_net_gnd_1_pin : out std_logic;
    fpga_0_net_gnd_2_pin : out std_logic;
    fpga_0_net_gnd_3_pin : out std_logic;
    fpga_0_net_gnd_4_pin : out std_logic;
    fpga_0_net_gnd_5_pin : out std_logic;
    fpga_0_net_gnd_6_pin : out std_logic;
    sys_clk_pin : in std_logic;
    sys_rst_pin : in std_logic;
    myfirewall_0_ppc_ce_n_conf_pin : out std_logic;
    myfirewall_0_ppc_we_n_conf_pin : out std_logic;
    myfirewall_0_ppc_re_n_conf_pin : out std_logic;
    myfirewall_0_ppc_clr_n_conf_pin : out std_logic;
    myfirewall_0_ppc_addr_conf_pin : out std_logic_vector(0 to 7);
    myfirewall_0_ppc_wdat_conf_pin : out std_logic_vector(0 to 15);
    myfirewall_0_conf_rdat_ppc_pin : in std_logic_vector(0 to 15)
  );
end system_stub;

architecture STRUCTURE of system_stub is

  component system is
    port (
      fpga_0_RS232_Uart_1_RX_pin : in std_logic;
      fpga_0_RS232_Uart_1_TX_pin : out std_logic;
      fpga_0_LEDs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
      fpga_0_DIPSWs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
      fpga_0_PushButtons_5Bit_GPIO_IO_pin : inout std_logic_vector(0 to 4);
      fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin : inout std_logic;
      fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin : inout std_logic;
      fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin : inout std_logic;
      fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin : inout std_logic;
      fpga_0_net_gnd_pin : out std_logic;
      fpga_0_net_gnd_1_pin : out std_logic;
      fpga_0_net_gnd_2_pin : out std_logic;
      fpga_0_net_gnd_3_pin : out std_logic;
      fpga_0_net_gnd_4_pin : out std_logic;
      fpga_0_net_gnd_5_pin : out std_logic;
      fpga_0_net_gnd_6_pin : out std_logic;
      sys_clk_pin : in std_logic;
      sys_rst_pin : in std_logic;
      myfirewall_0_ppc_ce_n_conf_pin : out std_logic;
      myfirewall_0_ppc_we_n_conf_pin : out std_logic;
      myfirewall_0_ppc_re_n_conf_pin : out std_logic;
      myfirewall_0_ppc_clr_n_conf_pin : out std_logic;
      myfirewall_0_ppc_addr_conf_pin : out std_logic_vector(0 to 7);
      myfirewall_0_ppc_wdat_conf_pin : out std_logic_vector(0 to 15);
      myfirewall_0_conf_rdat_ppc_pin : in std_logic_vector(0 to 15)
    );
  end component;

begin

  system_i : system
    port map (
      fpga_0_RS232_Uart_1_RX_pin => fpga_0_RS232_Uart_1_RX_pin,
      fpga_0_RS232_Uart_1_TX_pin => fpga_0_RS232_Uart_1_TX_pin,
      fpga_0_LEDs_4Bit_GPIO_IO_pin => fpga_0_LEDs_4Bit_GPIO_IO_pin,
      fpga_0_DIPSWs_4Bit_GPIO_IO_pin => fpga_0_DIPSWs_4Bit_GPIO_IO_pin,
      fpga_0_PushButtons_5Bit_GPIO_IO_pin => fpga_0_PushButtons_5Bit_GPIO_IO_pin,
      fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin => fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin,
      fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin => fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin,
      fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin => fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin,
      fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin => fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin,
      fpga_0_net_gnd_pin => fpga_0_net_gnd_pin,
      fpga_0_net_gnd_1_pin => fpga_0_net_gnd_1_pin,
      fpga_0_net_gnd_2_pin => fpga_0_net_gnd_2_pin,
      fpga_0_net_gnd_3_pin => fpga_0_net_gnd_3_pin,
      fpga_0_net_gnd_4_pin => fpga_0_net_gnd_4_pin,
      fpga_0_net_gnd_5_pin => fpga_0_net_gnd_5_pin,
      fpga_0_net_gnd_6_pin => fpga_0_net_gnd_6_pin,
      sys_clk_pin => sys_clk_pin,
      sys_rst_pin => sys_rst_pin,
      myfirewall_0_ppc_ce_n_conf_pin => myfirewall_0_ppc_ce_n_conf_pin,
      myfirewall_0_ppc_we_n_conf_pin => myfirewall_0_ppc_we_n_conf_pin,
      myfirewall_0_ppc_re_n_conf_pin => myfirewall_0_ppc_re_n_conf_pin,
      myfirewall_0_ppc_clr_n_conf_pin => myfirewall_0_ppc_clr_n_conf_pin,
      myfirewall_0_ppc_addr_conf_pin => myfirewall_0_ppc_addr_conf_pin,
      myfirewall_0_ppc_wdat_conf_pin => myfirewall_0_ppc_wdat_conf_pin,
      myfirewall_0_conf_rdat_ppc_pin => myfirewall_0_conf_rdat_ppc_pin
    );

end architecture STRUCTURE;