system.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

  output Sln_xferAck;
  output IP2INTC_Irpt;
  input [0:3] GPIO_in;
  output [0:3] GPIO_d_out;
  output [0:3] GPIO_t_out;
  input [0:3] GPIO2_in;
  output [0:3] GPIO2_d_out;
  output [0:3] GPIO2_t_out;
  input [0:3] GPIO_IO_I;
  output [0:3] GPIO_IO_O;
  output [0:3] GPIO_IO_T;
  input [0:3] GPIO2_IO_I;
  output [0:3] GPIO2_IO_O;
  output [0:3] GPIO2_IO_T;
endmodule

// synthesis attribute box_type of leds_4bit_wrapper is "black_box";

module dipsws_4bit_wrapper
  (
    OPB_ABus,
    OPB_BE,
    OPB_Clk,
    OPB_DBus,
    OPB_RNW,
    OPB_Rst,
    OPB_select,
    OPB_seqAddr,
    Sln_DBus,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Sln_xferAck,
    IP2INTC_Irpt,
    GPIO_in,
    GPIO_d_out,
    GPIO_t_out,
    GPIO2_in,
    GPIO2_d_out,
    GPIO2_t_out,
    GPIO_IO_I,
    GPIO_IO_O,
    GPIO_IO_T,
    GPIO2_IO_I,
    GPIO2_IO_O,
    GPIO2_IO_T
  );
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_Clk;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_Rst;
  input OPB_select;
  input OPB_seqAddr;
  output [0:31] Sln_DBus;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  output Sln_xferAck;
  output IP2INTC_Irpt;
  input [0:3] GPIO_in;
  output [0:3] GPIO_d_out;
  output [0:3] GPIO_t_out;
  input [0:3] GPIO2_in;
  output [0:3] GPIO2_d_out;
  output [0:3] GPIO2_t_out;
  input [0:3] GPIO_IO_I;
  output [0:3] GPIO_IO_O;
  output [0:3] GPIO_IO_T;
  input [0:3] GPIO2_IO_I;
  output [0:3] GPIO2_IO_O;
  output [0:3] GPIO2_IO_T;
endmodule

// synthesis attribute box_type of dipsws_4bit_wrapper is "black_box";

module pushbuttons_5bit_wrapper
  (
    OPB_ABus,
    OPB_BE,
    OPB_Clk,
    OPB_DBus,
    OPB_RNW,
    OPB_Rst,
    OPB_select,
    OPB_seqAddr,
    Sln_DBus,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Sln_xferAck,
    IP2INTC_Irpt,
    GPIO_in,
    GPIO_d_out,
    GPIO_t_out,
    GPIO2_in,
    GPIO2_d_out,
    GPIO2_t_out,
    GPIO_IO_I,
    GPIO_IO_O,
    GPIO_IO_T,
    GPIO2_IO_I,
    GPIO2_IO_O,
    GPIO2_IO_T
  );
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_Clk;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_Rst;
  input OPB_select;
  input OPB_seqAddr;
  output [0:31] Sln_DBus;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  output Sln_xferAck;
  output IP2INTC_Irpt;
  input [0:4] GPIO_in;
  output [0:4] GPIO_d_out;
  output [0:4] GPIO_t_out;
  input [0:4] GPIO2_in;
  output [0:4] GPIO2_d_out;
  output [0:4] GPIO2_t_out;
  input [0:4] GPIO_IO_I;
  output [0:4] GPIO_IO_O;
  output [0:4] GPIO_IO_T;
  input [0:4] GPIO2_IO_I;
  output [0:4] GPIO2_IO_O;
  output [0:4] GPIO2_IO_T;
endmodule

// synthesis attribute box_type of pushbuttons_5bit_wrapper is "black_box";

module ps2_ports_wrapper
  (
    OPB_BE,
    IPIF_Rst,
    OPB_Select,
    OPB_DBus,
    OPB_Clk,
    OPB_ABus,
    OPB_RNW,
    OPB_seqAddr,
    Sys_Intr1,
    Sys_Intr2,
    Sln_XferAck,
    Sln_DBus,
    Sln_DBusEn,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Clkin1,
    Clkpd1,
    Rx1,
    Txpd1,
    Clkin2,
    Clkpd2,
    Rx2,
    Txpd2
  );
  input [0:3] OPB_BE;
  input IPIF_Rst;
  input OPB_Select;
  input [0:31] OPB_DBus;
  input OPB_Clk;
  input [0:31] OPB_ABus;
  input OPB_RNW;
  input OPB_seqAddr;
  output Sys_Intr1;
  output Sys_Intr2;
  output Sln_XferAck;
  output [0:31] Sln_DBus;
  output Sln_DBusEn;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  input Clkin1;
  output Clkpd1;
  input Rx1;
  output Txpd1;
  input Clkin2;
  output Clkpd2;
  input Rx2;
  output Txpd2;
endmodule

// synthesis attribute box_type of ps2_ports_wrapper is "black_box";

module plb_bram_if_cntlr_1_wrapper
  (
    plb_clk,
    plb_rst,
    plb_abort,
    plb_abus,
    plb_be,
    plb_buslock,
    plb_compress,
    plb_guarded,
    plb_lockerr,
    plb_masterid,
    plb_msize,
    plb_ordered,
    plb_pavalid,
    plb_rnw,
    plb_size,
    plb_type,
    sl_addrack,
    sl_mbusy,
    sl_merr,
    sl_rearbitrate,
    sl_ssize,
    sl_wait,
    plb_rdprim,
    plb_savalid,
    plb_wrprim,
    plb_wrburst,
    plb_wrdbus,
    sl_wrbterm,
    sl_wrcomp,
    sl_wrdack,
    plb_rdburst,
    sl_rdbterm,
    sl_rdcomp,
    sl_rddack,
    sl_rddbus,
    sl_rdwdaddr,
    plb_pendreq,
    plb_pendpri,
    plb_reqpri,
    bram_rst,
    bram_clk,
    bram_en,
    bram_wen,
    bram_addr,
    bram_din,
    bram_dout
  );
  input plb_clk;
  input plb_rst;
  input plb_abort;
  input [0:31] plb_abus;
  input [0:7] plb_be;
  input plb_buslock;
  input plb_compress;
  input plb_guarded;
  input plb_lockerr;
  input [0:0] plb_masterid;
  input [0:1] plb_msize;
  input plb_ordered;
  input plb_pavalid;
  input plb_rnw;
  input [0:3] plb_size;
  input [0:2] plb_type;
  output sl_addrack;
  output [0:1] sl_mbusy;
  output [0:1] sl_merr;
  output sl_rearbitrate;
  output [0:1] sl_ssize;
  output sl_wait;
  input plb_rdprim;
  input plb_savalid;
  input plb_wrprim;
  input plb_wrburst;
  input [0:63] plb_wrdbus;
  output sl_wrbterm;
  output sl_wrcomp;
  output sl_wrdack;
  input plb_rdburst;
  output sl_rdbterm;
  output sl_rdcomp;
  output sl_rddack;
  output [0:63] sl_rddbus;
  output [0:3] sl_rdwdaddr;
  input plb_pendreq;
  input [0:1] plb_pendpri;
  input [0:1] plb_reqpri;
  output bram_rst;
  output bram_clk;
  output bram_en;
  output [0:7] bram_wen;
  output [0:31] bram_addr;
  input [0:63] bram_din;
  output [0:63] bram_dout;
endmodule

// synthesis attribute box_type of plb_bram_if_cntlr_1_wrapper is "black_box";

module plb_bram_if_cntlr_1_bram_wrapper
  (
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Addr_A,
    BRAM_Din_A,
    BRAM_Dout_A,
    BRAM_Rst_B,
    BRAM_Clk_B,
    BRAM_EN_B,
    BRAM_WEN_B,
    BRAM_Addr_B,
    BRAM_Din_B,
    BRAM_Dout_B
  );
  input BRAM_Rst_A;
  input BRAM_Clk_A;
  input BRAM_EN_A;
  input [0:7] BRAM_WEN_A;
  input [0:31] BRAM_Addr_A;
  output [0:63] BRAM_Din_A;
  input [0:63] BRAM_Dout_A;
  input BRAM_Rst_B;
  input BRAM_Clk_B;
  input BRAM_EN_B;
  input [0:7] BRAM_WEN_B;
  input [0:31] BRAM_Addr_B;
  output [0:63] BRAM_Din_B;
  input [0:63] BRAM_Dout_B;
endmodule

// synthesis attribute box_type of plb_bram_if_cntlr_1_bram_wrapper is "black_box";

module ps2_ports_io_adapter_wrapper
  (
    ps2_clk_tx_1,
    ps2_clk_rx_1,
    ps2_d_tx_1,
    ps2_d_rx_1,
    ps2_clk_tx_2,
    ps2_clk_rx_2,
    ps2_d_tx_2,
    ps2_d_rx_2,
    ps2_mouse_clk_I,
    ps2_mouse_clk_O,
    ps2_mouse_clk_T,
    ps2_mouse_data_I,
    ps2_mouse_data_O,
    ps2_mouse_data_T,
    ps2_keyb_clk_I,
    ps2_keyb_clk_O,
    ps2_keyb_clk_T,
    ps2_keyb_data_I,
    ps2_keyb_data_O,
    ps2_keyb_data_T
  );
  input ps2_clk_tx_1;
  output ps2_clk_rx_1;
  input ps2_d_tx_1;
  output ps2_d_rx_1;
  input ps2_clk_tx_2;
  output ps2_clk_rx_2;
  input ps2_d_tx_2;
  output ps2_d_rx_2;
  input ps2_mouse_clk_I;
  output ps2_mouse_clk_O;
  output ps2_mouse_clk_T;
  input ps2_mouse_data_I;
  output ps2_mouse_data_O;
  output ps2_mouse_data_T;
  input ps2_keyb_clk_I;
  output ps2_keyb_clk_O;
  output ps2_keyb_clk_T;
  input ps2_keyb_data_I;
  output ps2_keyb_data_O;
  output ps2_keyb_data_T;
endmodule

// synthesis attribute box_type of ps2_ports_io_adapter_wrapper is "black_box";

module dcm_0_wrapper
  (
    RST,
    CLKIN,
    CLKFB,
    PSEN,
    PSINCDEC,
    PSCLK,
    DSSEN,
    CLK0,
    CLK90,
    CLK180,
    CLK270,
    CLKDV,
    CLK2X,
    CLK2X180,
    CLKFX,
    CLKFX180,
    STATUS,
    LOCKED,
    PSDONE
  );
  input RST;
  input CLKIN;
  input CLKFB;
  input PSEN;
  input PSINCDEC;
  input PSCLK;
  input DSSEN;
  output CLK0;
  output CLK90;
  output CLK180;
  output CLK270;
  output CLKDV;
  output CLK2X;
  output CLK2X180;
  output CLKFX;
  output CLKFX180;
  output [7:0] STATUS;
  output LOCKED;
  output PSDONE;
endmodule

// synthesis attribute box_type of dcm_0_wrapper is "black_box";

module myfirewall_0_wrapper
  (
    sys_clk_in_100m,
    sys_rst_in,
    ppc_ce_n_conf,
    ppc_we_n_conf,
    ppc_re_n_conf,
    ppc_clr_n_conf,
    ppc_addr_conf,
    ppc_wdat_conf,
    conf_rdat_ppc,
    OPB_Clk,
    OPB_Rst,
    Sl_DBus,
    Sl_errAck,
    Sl_retry,
    Sl_toutSup,
    Sl_xferAck,
    OPB_ABus,
    OPB_BE,
    OPB_DBus,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr
  );
  input sys_clk_in_100m;
  input sys_rst_in;
  output ppc_ce_n_conf;
  output ppc_we_n_conf;
  output ppc_re_n_conf;
  output ppc_clr_n_conf;
  output [0:7] ppc_addr_conf;
  output [0:15] ppc_wdat_conf;
  input [0:15] conf_rdat_ppc;
  input OPB_Clk;
  input OPB_Rst;
  output [0:31] Sl_DBus;
  output Sl_errAck;
  output Sl_retry;
  output Sl_toutSup;
  output Sl_xferAck;
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
endmodule

// synthesis attribute box_type of myfirewall_0_wrapper is "black_box";