system.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

    PLB_ABus,
    PLB_BE,
    PLB_MAddrAck,
    PLB_MBusy,
    PLB_MErr,
    PLB_MRdBTerm,
    PLB_MRdDAck,
    PLB_MRdDBus,
    PLB_MRdWdAddr,
    PLB_MRearbitrate,
    PLB_MWrBTerm,
    PLB_MWrDAck,
    PLB_MSSize,
    PLB_PAValid,
    PLB_RNW,
    PLB_SAValid,
    PLB_abort,
    PLB_busLock,
    PLB_compress,
    PLB_guarded,
    PLB_lockErr,
    PLB_masterID,
    PLB_MSize,
    PLB_ordered,
    PLB_pendPri,
    PLB_pendReq,
    PLB_rdBurst,
    PLB_rdPrim,
    PLB_reqPri,
    PLB_size,
    PLB_type,
    PLB_wrBurst,
    PLB_wrDBus,
    PLB_wrPrim,
    PLB_SaddrAck,
    PLB_SMErr,
    PLB_SMBusy,
    PLB_SrdBTerm,
    PLB_SrdComp,
    PLB_SrdDAck,
    PLB_SrdDBus,
    PLB_SrdWdAddr,
    PLB_Srearbitrate,
    PLB_Sssize,
    PLB_Swait,
    PLB_SwrBTerm,
    PLB_SwrComp,
    PLB_SwrDAck,
    PLB2OPB_rearb,
    ArbAddrVldReg,
    Bus_Error_Det
  );
  input PLB_Clk;
  input SYS_Rst;
  output PLB_Rst;
  output PLB_dcrAck;
  output [0:31] PLB_dcrDBus;
  input [0:9] DCR_ABus;
  input [0:31] DCR_DBus;
  input DCR_Read;
  input DCR_Write;
  input [0:63] M_ABus;
  input [0:15] M_BE;
  input [0:1] M_RNW;
  input [0:1] M_abort;
  input [0:1] M_busLock;
  input [0:1] M_compress;
  input [0:1] M_guarded;
  input [0:1] M_lockErr;
  input [0:3] M_MSize;
  input [0:1] M_ordered;
  input [0:3] M_priority;
  input [0:1] M_rdBurst;
  input [0:1] M_request;
  input [0:7] M_size;
  input [0:5] M_type;
  input [0:1] M_wrBurst;
  input [0:127] M_wrDBus;
  input [0:1] Sl_addrAck;
  input [0:3] Sl_MErr;
  input [0:3] Sl_MBusy;
  input [0:1] Sl_rdBTerm;
  input [0:1] Sl_rdComp;
  input [0:1] Sl_rdDAck;
  input [0:127] Sl_rdDBus;
  input [0:7] Sl_rdWdAddr;
  input [0:1] Sl_rearbitrate;
  input [0:3] Sl_SSize;
  input [0:1] Sl_wait;
  input [0:1] Sl_wrBTerm;
  input [0:1] Sl_wrComp;
  input [0:1] Sl_wrDAck;
  output [0:31] PLB_ABus;
  output [0:7] PLB_BE;
  output [0:1] PLB_MAddrAck;
  output [0:1] PLB_MBusy;
  output [0:1] PLB_MErr;
  output [0:1] PLB_MRdBTerm;
  output [0:1] PLB_MRdDAck;
  output [0:127] PLB_MRdDBus;
  output [0:7] PLB_MRdWdAddr;
  output [0:1] PLB_MRearbitrate;
  output [0:1] PLB_MWrBTerm;
  output [0:1] PLB_MWrDAck;
  output [0:3] PLB_MSSize;
  output PLB_PAValid;
  output PLB_RNW;
  output PLB_SAValid;
  output PLB_abort;
  output PLB_busLock;
  output PLB_compress;
  output PLB_guarded;
  output PLB_lockErr;
  output [0:0] PLB_masterID;
  output [0:1] PLB_MSize;
  output PLB_ordered;
  output [0:1] PLB_pendPri;
  output PLB_pendReq;
  output PLB_rdBurst;
  output PLB_rdPrim;
  output [0:1] PLB_reqPri;
  output [0:3] PLB_size;
  output [0:2] PLB_type;
  output PLB_wrBurst;
  output [0:63] PLB_wrDBus;
  output PLB_wrPrim;
  output PLB_SaddrAck;
  output [0:1] PLB_SMErr;
  output [0:1] PLB_SMBusy;
  output PLB_SrdBTerm;
  output PLB_SrdComp;
  output PLB_SrdDAck;
  output [0:63] PLB_SrdDBus;
  output [0:3] PLB_SrdWdAddr;
  output PLB_Srearbitrate;
  output [0:1] PLB_Sssize;
  output PLB_Swait;
  output PLB_SwrBTerm;
  output PLB_SwrComp;
  output PLB_SwrDAck;
  input [0:1] PLB2OPB_rearb;
  output ArbAddrVldReg;
  output Bus_Error_Det;
endmodule

// synthesis attribute box_type of plb_wrapper is "black_box";

module opb_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    SYS_Rst,
    Debug_SYS_Rst,
    WDT_Rst,
    M_ABus,
    M_BE,
    M_beXfer,
    M_busLock,
    M_DBus,
    M_DBusEn,
    M_DBusEn32_63,
    M_dwXfer,
    M_fwXfer,
    M_hwXfer,
    M_request,
    M_RNW,
    M_select,
    M_seqAddr,
    Sl_beAck,
    Sl_DBus,
    Sl_DBusEn,
    Sl_DBusEn32_63,
    Sl_errAck,
    Sl_dwAck,
    Sl_fwAck,
    Sl_hwAck,
    Sl_retry,
    Sl_toutSup,
    Sl_xferAck,
    OPB_MRequest,
    OPB_ABus,
    OPB_BE,
    OPB_beXfer,
    OPB_beAck,
    OPB_busLock,
    OPB_rdDBus,
    OPB_wrDBus,
    OPB_DBus,
    OPB_errAck,
    OPB_dwAck,
    OPB_dwXfer,
    OPB_fwAck,
    OPB_fwXfer,
    OPB_hwAck,
    OPB_hwXfer,
    OPB_MGrant,
    OPB_pendReq,
    OPB_retry,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_timeout,
    OPB_toutSup,
    OPB_xferAck
  );
  input OPB_Clk;
  output OPB_Rst;
  input SYS_Rst;
  input Debug_SYS_Rst;
  input WDT_Rst;
  input [0:31] M_ABus;
  input [0:3] M_BE;
  input [0:0] M_beXfer;
  input [0:0] M_busLock;
  input [0:31] M_DBus;
  input [0:0] M_DBusEn;
  input [0:0] M_DBusEn32_63;
  input [0:0] M_dwXfer;
  input [0:0] M_fwXfer;
  input [0:0] M_hwXfer;
  input [0:0] M_request;
  input [0:0] M_RNW;
  input [0:0] M_select;
  input [0:0] M_seqAddr;
  input [0:5] Sl_beAck;
  input [0:191] Sl_DBus;
  input [0:5] Sl_DBusEn;
  input [0:5] Sl_DBusEn32_63;
  input [0:5] Sl_errAck;
  input [0:5] Sl_dwAck;
  input [0:5] Sl_fwAck;
  input [0:5] Sl_hwAck;
  input [0:5] Sl_retry;
  input [0:5] Sl_toutSup;
  input [0:5] Sl_xferAck;
  output [0:0] OPB_MRequest;
  output [0:31] OPB_ABus;
  output [0:3] OPB_BE;
  output OPB_beXfer;
  output OPB_beAck;
  output OPB_busLock;
  output [0:31] OPB_rdDBus;
  output [0:31] OPB_wrDBus;
  output [0:31] OPB_DBus;
  output OPB_errAck;
  output OPB_dwAck;
  output OPB_dwXfer;
  output OPB_fwAck;
  output OPB_fwXfer;
  output OPB_hwAck;
  output OPB_hwXfer;
  output [0:0] OPB_MGrant;
  output [0:0] OPB_pendReq;
  output OPB_retry;
  output OPB_RNW;
  output OPB_select;
  output OPB_seqAddr;
  output OPB_timeout;
  output OPB_toutSup;
  output OPB_xferAck;
endmodule

// synthesis attribute box_type of opb_wrapper is "black_box";

module plb2opb_wrapper
  (
    PLB_Clk,
    OPB_Clk,
    PLB_Rst,
    OPB_Rst,
    Bus_Error_Det,
    BGI_Trans_Abort,
    BGO_dcrAck,
    BGO_dcrDBus,
    DCR_ABus,
    DCR_DBus,
    DCR_Read,
    DCR_Write,
    BGO_addrAck,
    BGO_MErr,
    BGO_MBusy,
    BGO_rdBTerm,
    BGO_rdComp,
    BGO_rdDAck,
    BGO_rdDBus,
    BGO_rdWdAddr,
    BGO_rearbitrate,
    BGO_SSize,
    BGO_wait,
    BGO_wrBTerm,
    BGO_wrComp,
    BGO_wrDAck,
    PLB_abort,
    PLB_ABus,
    PLB_BE,
    PLB_busLock,
    PLB_compress,
    PLB_guarded,
    PLB_lockErr,
    PLB_masterID,
    PLB_MSize,
    PLB_ordered,
    PLB_PAValid,
    PLB_rdBurst,
    PLB_rdPrim,
    PLB_RNW,
    PLB_SAValid,
    PLB_size,
    PLB_type,
    PLB_wrBurst,
    PLB_wrDBus,
    PLB_wrPrim,
    PLB2OPB_rearb,
    BGO_ABus,
    BGO_BE,
    BGO_busLock,
    BGO_DBus,
    BGO_request,
    BGO_RNW,
    BGO_select,
    BGO_seqAddr,
    OPB_DBus,
    OPB_errAck,
    OPB_MnGrant,
    OPB_retry,
    OPB_timeout,
    OPB_xferAck
  );
  input PLB_Clk;
  input OPB_Clk;
  input PLB_Rst;
  input OPB_Rst;
  output Bus_Error_Det;
  output BGI_Trans_Abort;
  output BGO_dcrAck;
  output [0:31] BGO_dcrDBus;
  input [0:9] DCR_ABus;
  input [0:31] DCR_DBus;
  input DCR_Read;
  input DCR_Write;
  output BGO_addrAck;
  output [0:1] BGO_MErr;
  output [0:1] BGO_MBusy;
  output BGO_rdBTerm;
  output BGO_rdComp;
  output BGO_rdDAck;
  output [0:63] BGO_rdDBus;
  output [0:3] BGO_rdWdAddr;
  output BGO_rearbitrate;
  output [0:1] BGO_SSize;
  output BGO_wait;
  output BGO_wrBTerm;
  output BGO_wrComp;
  output BGO_wrDAck;
  input PLB_abort;
  input [0:31] PLB_ABus;
  input [0:7] PLB_BE;
  input PLB_busLock;
  input PLB_compress;
  input PLB_guarded;
  input PLB_lockErr;
  input [0:0] PLB_masterID;
  input [0:1] PLB_MSize;
  input PLB_ordered;
  input PLB_PAValid;
  input PLB_rdBurst;
  input PLB_rdPrim;
  input PLB_RNW;
  input PLB_SAValid;
  input [0:3] PLB_size;
  input [0:2] PLB_type;
  input PLB_wrBurst;
  input [0:63] PLB_wrDBus;
  input PLB_wrPrim;
  output PLB2OPB_rearb;
  output [0:31] BGO_ABus;
  output [0:3] BGO_BE;
  output BGO_busLock;
  output [0:31] BGO_DBus;
  output BGO_request;
  output BGO_RNW;
  output BGO_select;
  output BGO_seqAddr;
  input [0:31] OPB_DBus;
  input OPB_errAck;
  input OPB_MnGrant;
  input OPB_retry;
  input OPB_timeout;
  input OPB_xferAck;
endmodule

// synthesis attribute box_type of plb2opb_wrapper is "black_box";

module rs232_uart_1_wrapper
  (
    OPB_Clk,
    OPB_Rst,
    Interrupt,
    OPB_ABus,
    OPB_BE,
    OPB_RNW,
    OPB_select,
    OPB_seqAddr,
    OPB_DBus,
    UART_DBus,
    UART_errAck,
    UART_retry,
    UART_toutSup,
    UART_xferAck,
    RX,
    TX
  );
  input OPB_Clk;
  input OPB_Rst;
  output Interrupt;
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_RNW;
  input OPB_select;
  input OPB_seqAddr;
  input [0:31] OPB_DBus;
  output [0:31] UART_DBus;
  output UART_errAck;
  output UART_retry;
  output UART_toutSup;
  output UART_xferAck;
  input RX;
  output TX;
endmodule

// synthesis attribute box_type of rs232_uart_1_wrapper is "black_box";

module leds_4bit_wrapper
  (
    OPB_ABus,
    OPB_BE,
    OPB_Clk,
    OPB_DBus,
    OPB_RNW,
    OPB_Rst,
    OPB_select,
    OPB_seqAddr,
    Sln_DBus,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Sln_xferAck,
    IP2INTC_Irpt,
    GPIO_in,
    GPIO_d_out,
    GPIO_t_out,
    GPIO2_in,
    GPIO2_d_out,
    GPIO2_t_out,
    GPIO_IO_I,
    GPIO_IO_O,
    GPIO_IO_T,
    GPIO2_IO_I,
    GPIO2_IO_O,
    GPIO2_IO_T
  );
  input [0:31] OPB_ABus;
  input [0:3] OPB_BE;
  input OPB_Clk;
  input [0:31] OPB_DBus;
  input OPB_RNW;
  input OPB_Rst;
  input OPB_select;
  input OPB_seqAddr;
  output [0:31] Sln_DBus;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;