system.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

      .T ( fpga_0_LEDs_4Bit_GPIO_IO_T[3] )
    );

  IOBUF
    iobuf_4 (
      .I ( fpga_0_DIPSWs_4Bit_GPIO_IO_O[0] ),
      .IO ( fpga_0_DIPSWs_4Bit_GPIO_IO_pin[0] ),
      .O ( fpga_0_DIPSWs_4Bit_GPIO_IO_I[0] ),
      .T ( fpga_0_DIPSWs_4Bit_GPIO_IO_T[0] )
    );

  IOBUF
    iobuf_5 (
      .I ( fpga_0_DIPSWs_4Bit_GPIO_IO_O[1] ),
      .IO ( fpga_0_DIPSWs_4Bit_GPIO_IO_pin[1] ),
      .O ( fpga_0_DIPSWs_4Bit_GPIO_IO_I[1] ),
      .T ( fpga_0_DIPSWs_4Bit_GPIO_IO_T[1] )
    );

  IOBUF
    iobuf_6 (
      .I ( fpga_0_DIPSWs_4Bit_GPIO_IO_O[2] ),
      .IO ( fpga_0_DIPSWs_4Bit_GPIO_IO_pin[2] ),
      .O ( fpga_0_DIPSWs_4Bit_GPIO_IO_I[2] ),
      .T ( fpga_0_DIPSWs_4Bit_GPIO_IO_T[2] )
    );

  IOBUF
    iobuf_7 (
      .I ( fpga_0_DIPSWs_4Bit_GPIO_IO_O[3] ),
      .IO ( fpga_0_DIPSWs_4Bit_GPIO_IO_pin[3] ),
      .O ( fpga_0_DIPSWs_4Bit_GPIO_IO_I[3] ),
      .T ( fpga_0_DIPSWs_4Bit_GPIO_IO_T[3] )
    );

  IOBUF
    iobuf_8 (
      .I ( fpga_0_PushButtons_5Bit_GPIO_IO_O[0] ),
      .IO ( fpga_0_PushButtons_5Bit_GPIO_IO_pin[0] ),
      .O ( fpga_0_PushButtons_5Bit_GPIO_IO_I[0] ),
      .T ( fpga_0_PushButtons_5Bit_GPIO_IO_T[0] )
    );

  IOBUF
    iobuf_9 (
      .I ( fpga_0_PushButtons_5Bit_GPIO_IO_O[1] ),
      .IO ( fpga_0_PushButtons_5Bit_GPIO_IO_pin[1] ),
      .O ( fpga_0_PushButtons_5Bit_GPIO_IO_I[1] ),
      .T ( fpga_0_PushButtons_5Bit_GPIO_IO_T[1] )
    );

  IOBUF
    iobuf_10 (
      .I ( fpga_0_PushButtons_5Bit_GPIO_IO_O[2] ),
      .IO ( fpga_0_PushButtons_5Bit_GPIO_IO_pin[2] ),
      .O ( fpga_0_PushButtons_5Bit_GPIO_IO_I[2] ),
      .T ( fpga_0_PushButtons_5Bit_GPIO_IO_T[2] )
    );

  IOBUF
    iobuf_11 (
      .I ( fpga_0_PushButtons_5Bit_GPIO_IO_O[3] ),
      .IO ( fpga_0_PushButtons_5Bit_GPIO_IO_pin[3] ),
      .O ( fpga_0_PushButtons_5Bit_GPIO_IO_I[3] ),
      .T ( fpga_0_PushButtons_5Bit_GPIO_IO_T[3] )
    );

  IOBUF
    iobuf_12 (
      .I ( fpga_0_PushButtons_5Bit_GPIO_IO_O[4] ),
      .IO ( fpga_0_PushButtons_5Bit_GPIO_IO_pin[4] ),
      .O ( fpga_0_PushButtons_5Bit_GPIO_IO_I[4] ),
      .T ( fpga_0_PushButtons_5Bit_GPIO_IO_T[4] )
    );

  IOBUF
    iobuf_13 (
      .I ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_O ),
      .IO ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin ),
      .O ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_I ),
      .T ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_T )
    );

  IOBUF
    iobuf_14 (
      .I ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_O ),
      .IO ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin ),
      .O ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_I ),
      .T ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_T )
    );

  IOBUF
    iobuf_15 (
      .I ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_O ),
      .IO ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin ),
      .O ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_I ),
      .T ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_T )
    );

  IOBUF
    iobuf_16 (
      .I ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_O ),
      .IO ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin ),
      .O ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_I ),
      .T ( fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_T )
    );

endmodule

module ppc405_0_wrapper
  (
    C405CPMCORESLEEPREQ,
    C405CPMMSRCE,
    C405CPMMSREE,
    C405CPMTIMERIRQ,
    C405CPMTIMERRESETREQ,
    C405XXXMACHINECHECK,
    CPMC405CLOCK,
    CPMC405CORECLKINACTIVE,
    CPMC405CPUCLKEN,
    CPMC405JTAGCLKEN,
    CPMC405TIMERCLKEN,
    CPMC405TIMERTICK,
    MCBCPUCLKEN,
    MCBTIMEREN,
    MCPPCRST,
    PLBCLK,
    DCRCLK,
    C405RSTCHIPRESETREQ,
    C405RSTCORERESETREQ,
    C405RSTSYSRESETREQ,
    RSTC405RESETCHIP,
    RSTC405RESETCORE,
    RSTC405RESETSYS,
    C405PLBICUABUS,
    C405PLBICUBE,
    C405PLBICURNW,
    C405PLBICUABORT,
    C405PLBICUBUSLOCK,
    C405PLBICUU0ATTR,
    C405PLBICUGUARDED,
    C405PLBICULOCKERR,
    C405PLBICUMSIZE,
    C405PLBICUORDERED,
    C405PLBICUPRIORITY,
    C405PLBICURDBURST,
    C405PLBICUREQUEST,
    C405PLBICUSIZE,
    C405PLBICUTYPE,
    C405PLBICUWRBURST,
    C405PLBICUWRDBUS,
    C405PLBICUCACHEABLE,
    PLBC405ICUADDRACK,
    PLBC405ICUBUSY,
    PLBC405ICUERR,
    PLBC405ICURDBTERM,
    PLBC405ICURDDACK,
    PLBC405ICURDDBUS,
    PLBC405ICURDWDADDR,
    PLBC405ICUREARBITRATE,
    PLBC405ICUWRBTERM,
    PLBC405ICUWRDACK,
    PLBC405ICUSSIZE,
    PLBC405ICUSERR,
    PLBC405ICUSBUSYS,
    C405PLBDCUABUS,
    C405PLBDCUBE,
    C405PLBDCURNW,
    C405PLBDCUABORT,
    C405PLBDCUBUSLOCK,
    C405PLBDCUU0ATTR,
    C405PLBDCUGUARDED,
    C405PLBDCULOCKERR,
    C405PLBDCUMSIZE,
    C405PLBDCUORDERED,
    C405PLBDCUPRIORITY,
    C405PLBDCURDBURST,
    C405PLBDCUREQUEST,
    C405PLBDCUSIZE,
    C405PLBDCUTYPE,
    C405PLBDCUWRBURST,
    C405PLBDCUWRDBUS,
    C405PLBDCUCACHEABLE,
    C405PLBDCUWRITETHRU,
    PLBC405DCUADDRACK,
    PLBC405DCUBUSY,
    PLBC405DCUERR,
    PLBC405DCURDBTERM,
    PLBC405DCURDDACK,
    PLBC405DCURDDBUS,
    PLBC405DCURDWDADDR,
    PLBC405DCUREARBITRATE,
    PLBC405DCUWRBTERM,
    PLBC405DCUWRDACK,
    PLBC405DCUSSIZE,
    PLBC405DCUSERR,
    PLBC405DCUSBUSYS,
    BRAMDSOCMCLK,
    BRAMDSOCMRDDBUS,
    DSARCVALUE,
    DSCNTLVALUE,
    DSOCMBRAMABUS,
    DSOCMBRAMBYTEWRITE,
    DSOCMBRAMEN,
    DSOCMBRAMWRDBUS,
    DSOCMBUSY,
    BRAMISOCMCLK,
    BRAMISOCMRDDBUS,
    ISARCVALUE,
    ISCNTLVALUE,
    ISOCMBRAMEN,
    ISOCMBRAMEVENWRITEEN,
    ISOCMBRAMODDWRITEEN,
    ISOCMBRAMRDABUS,
    ISOCMBRAMWRABUS,
    ISOCMBRAMWRDBUS,
    C405DCRABUS,
    C405DCRDBUSOUT,
    C405DCRREAD,
    C405DCRWRITE,
    DCRC405ACK,
    DCRC405DBUSIN,
    EICC405CRITINPUTIRQ,
    EICC405EXTINPUTIRQ,
    C405JTGCAPTUREDR,
    C405JTGEXTEST,
    C405JTGPGMOUT,
    C405JTGSHIFTDR,
    C405JTGTDO,
    C405JTGTDOEN,
    C405JTGUPDATEDR,
    MCBJTAGEN,
    JTGC405BNDSCANTDO,
    JTGC405TCK,
    JTGC405TDI,
    JTGC405TMS,
    JTGC405TRSTNEG,
    C405DBGMSRWE,
    C405DBGSTOPACK,
    C405DBGWBCOMPLETE,
    C405DBGWBFULL,
    C405DBGWBIAR,
    DBGC405DEBUGHALT,
    DBGC405EXTBUSHOLDACK,
    DBGC405UNCONDDEBUGEVENT,
    C405TRCCYCLE,
    C405TRCEVENEXECUTIONSTATUS,
    C405TRCODDEXECUTIONSTATUS,
    C405TRCTRACESTATUS,
    C405TRCTRIGGEREVENTOUT,
    C405TRCTRIGGEREVENTTYPE,
    TRCC405TRACEDISABLE,
    TRCC405TRIGGEREVENTIN
  );
  output C405CPMCORESLEEPREQ;
  output C405CPMMSRCE;
  output C405CPMMSREE;
  output C405CPMTIMERIRQ;
  output C405CPMTIMERRESETREQ;
  output C405XXXMACHINECHECK;
  input CPMC405CLOCK;
  input CPMC405CORECLKINACTIVE;
  input CPMC405CPUCLKEN;
  input CPMC405JTAGCLKEN;
  input CPMC405TIMERCLKEN;
  input CPMC405TIMERTICK;
  input MCBCPUCLKEN;
  input MCBTIMEREN;
  input MCPPCRST;
  input PLBCLK;
  input DCRCLK;
  output C405RSTCHIPRESETREQ;
  output C405RSTCORERESETREQ;
  output C405RSTSYSRESETREQ;
  input RSTC405RESETCHIP;
  input RSTC405RESETCORE;
  input RSTC405RESETSYS;
  output [0:31] C405PLBICUABUS;
  output [0:7] C405PLBICUBE;
  output C405PLBICURNW;
  output C405PLBICUABORT;
  output C405PLBICUBUSLOCK;
  output C405PLBICUU0ATTR;
  output C405PLBICUGUARDED;
  output C405PLBICULOCKERR;
  output [0:1] C405PLBICUMSIZE;
  output C405PLBICUORDERED;
  output [0:1] C405PLBICUPRIORITY;
  output C405PLBICURDBURST;
  output C405PLBICUREQUEST;
  output [0:3] C405PLBICUSIZE;
  output [0:2] C405PLBICUTYPE;
  output C405PLBICUWRBURST;
  output [0:63] C405PLBICUWRDBUS;
  output C405PLBICUCACHEABLE;
  input PLBC405ICUADDRACK;
  input PLBC405ICUBUSY;
  input PLBC405ICUERR;
  input PLBC405ICURDBTERM;
  input PLBC405ICURDDACK;
  input [0:63] PLBC405ICURDDBUS;
  input [0:3] PLBC405ICURDWDADDR;
  input PLBC405ICUREARBITRATE;
  input PLBC405ICUWRBTERM;
  input PLBC405ICUWRDACK;
  input [0:1] PLBC405ICUSSIZE;
  input PLBC405ICUSERR;
  input PLBC405ICUSBUSYS;
  output [0:31] C405PLBDCUABUS;
  output [0:7] C405PLBDCUBE;
  output C405PLBDCURNW;
  output C405PLBDCUABORT;
  output C405PLBDCUBUSLOCK;
  output C405PLBDCUU0ATTR;
  output C405PLBDCUGUARDED;
  output C405PLBDCULOCKERR;
  output [0:1] C405PLBDCUMSIZE;
  output C405PLBDCUORDERED;
  output [0:1] C405PLBDCUPRIORITY;
  output C405PLBDCURDBURST;
  output C405PLBDCUREQUEST;
  output [0:3] C405PLBDCUSIZE;
  output [0:2] C405PLBDCUTYPE;
  output C405PLBDCUWRBURST;
  output [0:63] C405PLBDCUWRDBUS;
  output C405PLBDCUCACHEABLE;
  output C405PLBDCUWRITETHRU;
  input PLBC405DCUADDRACK;
  input PLBC405DCUBUSY;
  input PLBC405DCUERR;
  input PLBC405DCURDBTERM;
  input PLBC405DCURDDACK;
  input [0:63] PLBC405DCURDDBUS;
  input [0:3] PLBC405DCURDWDADDR;
  input PLBC405DCUREARBITRATE;
  input PLBC405DCUWRBTERM;
  input PLBC405DCUWRDACK;
  input [0:1] PLBC405DCUSSIZE;
  input PLBC405DCUSERR;
  input PLBC405DCUSBUSYS;
  input BRAMDSOCMCLK;
  input [0:31] BRAMDSOCMRDDBUS;
  input [0:7] DSARCVALUE;
  input [0:7] DSCNTLVALUE;
  output [8:29] DSOCMBRAMABUS;
  output [0:3] DSOCMBRAMBYTEWRITE;
  output DSOCMBRAMEN;
  output [0:31] DSOCMBRAMWRDBUS;
  output DSOCMBUSY;
  input BRAMISOCMCLK;
  input [0:63] BRAMISOCMRDDBUS;
  input [0:7] ISARCVALUE;
  input [0:7] ISCNTLVALUE;
  output ISOCMBRAMEN;
  output ISOCMBRAMEVENWRITEEN;
  output ISOCMBRAMODDWRITEEN;
  output [8:28] ISOCMBRAMRDABUS;
  output [8:28] ISOCMBRAMWRABUS;
  output [0:31] ISOCMBRAMWRDBUS;
  output [0:9] C405DCRABUS;
  output [0:31] C405DCRDBUSOUT;
  output C405DCRREAD;
  output C405DCRWRITE;
  input DCRC405ACK;
  input [0:31] DCRC405DBUSIN;
  input EICC405CRITINPUTIRQ;
  input EICC405EXTINPUTIRQ;
  output C405JTGCAPTUREDR;
  output C405JTGEXTEST;
  output C405JTGPGMOUT;
  output C405JTGSHIFTDR;
  output C405JTGTDO;
  output C405JTGTDOEN;
  output C405JTGUPDATEDR;
  input MCBJTAGEN;
  input JTGC405BNDSCANTDO;
  input JTGC405TCK;
  input JTGC405TDI;
  input JTGC405TMS;
  input JTGC405TRSTNEG;
  output C405DBGMSRWE;
  output C405DBGSTOPACK;
  output C405DBGWBCOMPLETE;
  output C405DBGWBFULL;
  output [0:29] C405DBGWBIAR;
  input DBGC405DEBUGHALT;
  input DBGC405EXTBUSHOLDACK;
  input DBGC405UNCONDDEBUGEVENT;
  output C405TRCCYCLE;
  output [0:1] C405TRCEVENEXECUTIONSTATUS;
  output [0:1] C405TRCODDEXECUTIONSTATUS;
  output [0:3] C405TRCTRACESTATUS;
  output C405TRCTRIGGEREVENTOUT;
  output [0:10] C405TRCTRIGGEREVENTTYPE;
  input TRCC405TRACEDISABLE;
  input TRCC405TRIGGEREVENTIN;
endmodule

// synthesis attribute box_type of ppc405_0_wrapper is "black_box";

module reset_block_wrapper
  (
    Slowest_sync_clk,
    Ext_Reset_In,
    Aux_Reset_In,
    Core_Reset_Req,
    Chip_Reset_Req,
    System_Reset_Req,
    Dcm_locked,
    Rstc405resetcore,
    Rstc405resetchip,
    Rstc405resetsys,
    Bus_Struct_Reset,
    Peripheral_Reset
  );
  input Slowest_sync_clk;
  input Ext_Reset_In;
  input Aux_Reset_In;
  input Core_Reset_Req;
  input Chip_Reset_Req;
  input System_Reset_Req;
  input Dcm_locked;
  output Rstc405resetcore;
  output Rstc405resetchip;
  output Rstc405resetsys;
  output [0:0] Bus_Struct_Reset;
  output [0:0] Peripheral_Reset;
endmodule

// synthesis attribute box_type of reset_block_wrapper is "black_box";

module plb_wrapper
  (
    PLB_Clk,
    SYS_Rst,
    PLB_Rst,
    PLB_dcrAck,
    PLB_dcrDBus,
    DCR_ABus,
    DCR_DBus,
    DCR_Read,
    DCR_Write,
    M_ABus,
    M_BE,
    M_RNW,
    M_abort,
    M_busLock,
    M_compress,
    M_guarded,
    M_lockErr,
    M_MSize,
    M_ordered,
    M_priority,
    M_rdBurst,
    M_request,
    M_size,
    M_type,
    M_wrBurst,
    M_wrDBus,
    Sl_addrAck,
    Sl_MErr,
    Sl_MBusy,
    Sl_rdBTerm,
    Sl_rdComp,
    Sl_rdDAck,
    Sl_rdDBus,
    Sl_rdWdAddr,
    Sl_rearbitrate,
    Sl_SSize,
    Sl_wait,
    Sl_wrBTerm,
    Sl_wrComp,
    Sl_wrDAck,