ps2_ports_wrapper.v

本系统由服务器软件控制平台和fpga硬件处理系统组成

//-----------------------------------------------------------------------------
// ps2_ports_wrapper.v
//-----------------------------------------------------------------------------

module ps2_ports_wrapper
  (
    OPB_BE,
    IPIF_Rst,
    OPB_Select,
    OPB_DBus,
    OPB_Clk,
    OPB_ABus,
    OPB_RNW,
    OPB_seqAddr,
    Sys_Intr1,
    Sys_Intr2,
    Sln_XferAck,
    Sln_DBus,
    Sln_DBusEn,
    Sln_errAck,
    Sln_retry,
    Sln_toutSup,
    Clkin1,
    Clkpd1,
    Rx1,
    Txpd1,
    Clkin2,
    Clkpd2,
    Rx2,
    Txpd2
  );
  input [0:3] OPB_BE;
  input IPIF_Rst;
  input OPB_Select;
  input [0:31] OPB_DBus;
  input OPB_Clk;
  input [0:31] OPB_ABus;
  input OPB_RNW;
  input OPB_seqAddr;
  output Sys_Intr1;
  output Sys_Intr2;
  output Sln_XferAck;
  output [0:31] Sln_DBus;
  output Sln_DBusEn;
  output Sln_errAck;
  output Sln_retry;
  output Sln_toutSup;
  input Clkin1;
  output Clkpd1;
  input Rx1;
  output Txpd1;
  input Clkin2;
  output Clkpd2;
  input Rx2;
  output Txpd2;

  defparam ps2_ports.C_BASEADDR = 'h7a400000;
  defparam ps2_ports.C_HIGHADDR = 'h7a40ffff;
  opb_ps2_dual_ref
    ps2_ports (
      .OPB_BE ( OPB_BE ),
      .IPIF_Rst ( IPIF_Rst ),
      .OPB_Select ( OPB_Select ),
      .OPB_DBus ( OPB_DBus ),
      .OPB_Clk ( OPB_Clk ),
      .OPB_ABus ( OPB_ABus ),
      .OPB_RNW ( OPB_RNW ),
      .OPB_seqAddr ( OPB_seqAddr ),
      .Sys_Intr1 ( Sys_Intr1 ),
      .Sys_Intr2 ( Sys_Intr2 ),
      .Sln_XferAck ( Sln_XferAck ),
      .Sln_DBus ( Sln_DBus ),
      .Sln_DBusEn ( Sln_DBusEn ),
      .Sln_errAck ( Sln_errAck ),
      .Sln_retry ( Sln_retry ),
      .Sln_toutSup ( Sln_toutSup ),
      .Clkin1 ( Clkin1 ),
      .Clkpd1 ( Clkpd1 ),
      .Rx1 ( Rx1 ),
      .Txpd1 ( Txpd1 ),
      .Clkin2 ( Clkin2 ),
      .Clkpd2 ( Clkpd2 ),
      .Rx2 ( Rx2 ),
      .Txpd2 ( Txpd2 )
    );

endmodule

// synthesis attribute x_core_info of ps2_ports_wrapper is opb_ps2_dual_ref_v1_00_a;