📄 user_logic.v
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//----------------------------------------------------------------------------
// user_logic.v - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. **
// ** **
// ** Xilinx, Inc. **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
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// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
// ** FOR A PARTICULAR PURPOSE. **
// ** **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: user_logic.v
// Version: 1.00.a
// Description: User logic module.
// Date: Sun Mar 23 22:21:57 2008 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
// --USER ports added here
sys_clk_in_100m,
sys_rst_in,
ppc_ce_n_conf,
ppc_we_n_conf,
ppc_re_n_conf,
ppc_clr_n_conf,
ppc_addr_conf,
ppc_wdat_conf,
conf_rdat_ppc,
// -- ADD USER PORTS ABOVE THIS LINE ---------------
// -- DO NOT EDIT BELOW THIS LINE ------------------
// -- Bus protocol ports, do not add to or delete
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Reset, // Bus to IP reset
Bus2IP_Addr, // Bus to IP address bus
Bus2IP_Data, // Bus to IP data bus for user logic
Bus2IP_BE, // Bus to IP byte enables for user logic
Bus2IP_RdCE, // Bus to IP read chip enable for user logic
Bus2IP_WrCE, // Bus to IP write chip enable for user logic
IP2Bus_Data, // IP to Bus data bus for user logic
IP2Bus_Ack, // IP to Bus acknowledgement
IP2Bus_Retry, // IP to Bus retry response
IP2Bus_Error, // IP to Bus error response
IP2Bus_ToutSup // IP to Bus timeout suppress
// -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_AWIDTH = 32;
parameter C_DWIDTH = 16;
parameter C_NUM_CE = 4;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
input sys_clk_in_100m;
input sys_rst_in;
output ppc_ce_n_conf;
output ppc_we_n_conf;
output ppc_re_n_conf;
output ppc_clr_n_conf;
output [7:0] ppc_addr_conf;
output [15:0] ppc_wdat_conf;
input [15:0] conf_rdat_ppc;
// -- ADD USER PORTS ABOVE THIS LINE -----------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input Bus2IP_Clk;
input Bus2IP_Reset;
input [0 : C_AWIDTH-1] Bus2IP_Addr;
input [0 : C_DWIDTH-1] Bus2IP_Data;
input [0 : C_DWIDTH/8-1] Bus2IP_BE;
input [0 : C_NUM_CE-1] Bus2IP_RdCE;
input [0 : C_NUM_CE-1] Bus2IP_WrCE;
output [0 : C_DWIDTH-1] IP2Bus_Data;
output IP2Bus_Ack;
output IP2Bus_Retry;
output IP2Bus_Error;
output IP2Bus_ToutSup;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// --USER nets declarations added here, as needed for user logic
// Nets for user logic slave model s/w accessible register example
reg [0 : C_DWIDTH-1] slv_reg0;
reg [0 : C_DWIDTH-1] slv_reg1;
reg [0 : C_DWIDTH-1] slv_reg2;
reg [0 : C_DWIDTH-1] slv_reg3;
wire [0 : 3] slv_reg_write_select;
wire [0 : 3] slv_reg_read_select;
reg [0 : C_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
// --USER logic implementation added here
wire sys_clk_in_100m;
wire sys_rst_in;
reg ppc_ce_n_conf;
reg ppc_we_n_conf;
reg ppc_re_n_conf;
reg ppc_clr_n_conf;
reg [7:0] ppc_addr_conf;
reg [15:0] ppc_wdat_conf;
wire [15:0] conf_rdat_ppc;
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible registers
//
// Note:
// The example code presented here is to show you one way of reading/writing
// software accessible registers implemented in the user logic slave model.
// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
// to one software accessible register by the top level template. For example,
// if you have four 32 bit software accessible registers in the user logic, you
// are basically operating on the following memory mapped registers:
//
// Bus2IP_WrCE or Memory Mapped
// Bus2IP_RdCE Register
// "1000" C_BASEADDR + 0x0
// "0100" C_BASEADDR + 0x4
// "0010" C_BASEADDR + 0x8
// "0001" C_BASEADDR + 0xC
//
// ------------------------------------------------------
assign
slv_reg_write_select = Bus2IP_WrCE[0:3],
slv_reg_read_select = Bus2IP_RdCE[0:3],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3];
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
//slv_reg3 <= 0;
end
else
case ( slv_reg_write_select )
4'b1000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
4'b0100 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
4'b0010 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
/* 4'b0001 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg3[bit_index] <= Bus2IP_Data[bit_index];*/
default : ;
endcase
end // SLAVE_REG_WRITE_PROC
// implement slave model register read mux
always @( slv_reg_read_select or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 )
begin: SLAVE_REG_READ_PROC
case ( slv_reg_read_select )
4'b1000 : slv_ip2bus_data <= slv_reg0;
4'b0100 : slv_ip2bus_data <= slv_reg1;
4'b0010 : slv_ip2bus_data <= slv_reg2;
4'b0001 : slv_ip2bus_data <= slv_reg3;
default : slv_ip2bus_data <= 0;
endcase
end // SLAVE_REG_READ_PROC
// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------
assign IP2Bus_Data = slv_ip2bus_data;
assign IP2Bus_Ack = slv_write_ack || slv_read_ack;
assign IP2Bus_Error = 0;
assign IP2Bus_Retry = 0;
assign IP2Bus_ToutSup = 0;
always @ (posedge sys_clk_in_100m or negedge sys_rst_in)
if(~sys_rst_in)
ppc_ce_n_conf <= 1;
else
ppc_ce_n_conf <= slv_reg0[0];
always @ (posedge sys_clk_in_100m or negedge sys_rst_in)
if(~sys_rst_in)
ppc_we_n_conf <= 1;
else
ppc_we_n_conf <= slv_reg0[1];
always @ (posedge sys_clk_in_100m or negedge sys_rst_in)
if(~sys_rst_in)
ppc_re_n_conf <= 1;
else
ppc_re_n_conf <= slv_reg0[2];
always @ (posedge sys_clk_in_100m or negedge sys_rst_in)
if(~sys_rst_in)
ppc_clr_n_conf <= 1;
else
ppc_clr_n_conf <= slv_reg0[3];
always @ (posedge sys_clk_in_100m or negedge sys_rst_in)
if(~sys_rst_in)
ppc_addr_conf <= 0;
else
ppc_addr_conf <= slv_reg1;
always @ (posedge sys_clk_in_100m or negedge sys_rst_in)
if(~sys_rst_in)
ppc_wdat_conf <= 0;
else
ppc_wdat_conf <= slv_reg2;
always @ (posedge sys_clk_in_100m or negedge sys_rst_in)
if(~sys_rst_in)
slv_reg3 <= 0;
else
slv_reg3 <= conf_rdat_ppc;
endmodule
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