ps2_ports_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_21> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_20> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_18> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_17> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_16> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_15> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_14> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_13> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_12> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_11> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_10> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_9> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_8> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_7> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_6> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_5> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_4> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_3> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_2> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_1> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_0> is unconnected in block <ps2_ports_wrapper>.
Building and optimizing final netlist ...
FlipFlop ps2_ports/IPIF/Bus2IP_Addr_19 has been replicated 1 time(s)

Final Macro Processing ...

Processing Unit <ps2_ports_wrapper> :
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <ps2_ports/ps2_I1/ps2_sie_I/clkin_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <ps2_ports/ps2_I1/ps2_sie_I/rx_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <ps2_ports/ps2_I2/ps2_sie_I/clkin_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <ps2_ports/ps2_I2/ps2_sie_I/rx_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <ps2_ports_wrapper> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 229
 Flip-Flops                                            : 229

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/ps2_ports_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 120

Cell Usage :
# BELS                             : 513
#      GND                         : 1
#      INV                         : 11
#      LUT1                        : 44
#      LUT2                        : 28
#      LUT2_D                      : 4
#      LUT3                        : 54
#      LUT3_D                      : 5
#      LUT3_L                      : 16
#      LUT4                        : 209
#      LUT4_D                      : 7
#      LUT4_L                      : 25
#      MUXCY                       : 51
#      MUXF5                       : 13
#      VCC                         : 1
#      XORCY                       : 44
# FlipFlops/Latches                : 229
#      FD                          : 12
#      FDR                         : 99
#      FDRE                        : 102
#      FDRS                        : 8
#      FDS                         : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                     216  out of  13696     1%  
 Number of Slice Flip Flops:           229  out of  27392     0%  
 Number of 4 input LUTs:               403  out of  27392     1%  
 Number of IOs:                        120
 Number of bonded IOBs:                  0  out of    556     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                          | Load  |
-----------------------------------+------------------------------------------------+-------+
OPB_Clk                            | NONE(ps2_ports/ps2_I1/ps2_reg_I/rx_data_fl_reg)| 229   |
-----------------------------------+------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 3.781ns (Maximum Frequency: 264.456MHz)
   Minimum input arrival time before clock: 2.488ns
   Maximum output required time after clock: 2.606ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'OPB_Clk'
  Clock period: 3.781ns (frequency: 264.456MHz)
  Total number of paths / destination ports: 2687 / 437
-------------------------------------------------------------------------
Delay:               3.781ns (Levels of Logic = 3)
  Source:            ps2_ports/IPIF/addr_hit (FF)
  Destination:       ps2_ports/ps2_I1/ps2_reg_I/int_rx_full_reg (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: ps2_ports/IPIF/addr_hit to ps2_ports/ps2_I1/ps2_reg_I/int_rx_full_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   0.370   0.564  ps2_ports/IPIF/addr_hit (ps2_ports/IPIF/addr_hit)
     LUT4:I0->O            2   0.275   0.514  ps2_ports/IPIF/Bus2IP_WrReq1_1 (ps2_ports/IPIF/Bus2IP_WrReq1)
     LUT2:I0->O           15   0.275   0.641  ps2_ports/_and00011 (ps2_ports/_and0001)
     LUT4:I2->O            1   0.275   0.331  ps2_ports/ps2_I1/ps2_reg_I/_or00181 (ps2_ports/ps2_I1/ps2_reg_I/_or0018)
     FDRE:R                    0.536          ps2_ports/ps2_I1/ps2_reg_I/intm_tx_noack_reg
    ----------------------------------------
    Total                      3.781ns (1.731ns logic, 2.050ns route)
                                       (45.8% logic, 54.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
  Total number of paths / destination ports: 333 / 249
-------------------------------------------------------------------------
Offset:              2.488ns (Levels of Logic = 8)
  Source:            OPB_ABus<9> (PAD)
  Destination:       ps2_ports/IPIF/gen_xfer_ack (FF)
  Destination Clock: OPB_Clk rising

  Data Path: OPB_ABus<9> to ps2_ports/IPIF/gen_xfer_ack
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I0->O            1   0.275   0.000  ps2_ports/IPIF/addr_decode_hit_wg_lut<1> (N3)
     MUXCY:S->O            1   0.334   0.000  ps2_ports/IPIF/addr_decode_hit_wg_cy<1> (ps2_ports/IPIF/addr_decode_hit_wg_cy<1>)
     MUXCY:CI->O           1   0.036   0.000  ps2_ports/IPIF/addr_decode_hit_wg_cy<2> (ps2_ports/IPIF/addr_decode_hit_wg_cy<2>)
     MUXCY:CI->O           1   0.036   0.000  ps2_ports/IPIF/addr_decode_hit_wg_cy<3> (ps2_ports/IPIF/addr_decode_hit_wg_cy<3>)
     MUXCY:CI->O           1   0.036   0.000  ps2_ports/IPIF/addr_decode_hit_wg_cy<4> (ps2_ports/IPIF/addr_decode_hit_wg_cy<4>)
     MUXCY:CI->O           1   0.036   0.000  ps2_ports/IPIF/addr_decode_hit_wg_cy<5> (ps2_ports/IPIF/addr_decode_hit_wg_cy<5>)
     MUXCY:CI->O           2   0.599   0.514  ps2_ports/IPIF/addr_decode_hit_wg_cy<6> (ps2_ports/IPIF/addr_decode_hit_wg_cy<6>)
     LUT4:I0->O            1   0.275   0.000  ps2_ports/IPIF/_and00001 (ps2_ports/IPIF/_and0000)
     FDR:D                     0.208          ps2_ports/IPIF/gen_xfer_ack
    ----------------------------------------
    Total                      2.488ns (1.974ns logic, 0.514ns route)
                                       (79.3% logic, 20.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
  Total number of paths / destination ports: 37 / 15
-------------------------------------------------------------------------
Offset:              2.606ns (Levels of Logic = 3)
  Source:            ps2_ports/ps2_I1/ps2_reg_I/int_wdt_tout_reg (FF)
  Destination:       Sys_Intr1 (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: ps2_ports/ps2_I1/ps2_reg_I/int_wdt_tout_reg to Sys_Intr1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   0.370   0.514  ps2_ports/ps2_I1/ps2_reg_I/int_wdt_tout_reg (ps2_ports/ps2_I1/ps2_reg_I/int_wdt_tout_q)
     LUT4:I0->O            1   0.275   0.467  ps2_ports/ps2_I1/ps2_reg_I/IP2Bus_Intr9 (ps2_ports/ps2_I1/ps2_reg_I/IP2Bus_Intr_map16)
     LUT3:I0->O            1   0.275   0.429  ps2_ports/ps2_I1/ps2_reg_I/IP2Bus_Intr22_SW0 (N1971)
     LUT4:I1->O            0   0.275   0.000  ps2_ports/ps2_I1/ps2_reg_I/IP2Bus_Intr22 (Sys_Intr1)
    ----------------------------------------
    Total                      2.606ns (1.195ns logic, 1.411ns route)
                                       (45.9% logic, 54.1% route)

=========================================================================
CPU : 61.81 / 62.13 s | Elapsed : 61.00 / 62.00 s
 
--> 

Total memory usage is 184192 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   40 (   0 filtered)
Number of infos    :    5 (   0 filtered)