ps2_ports_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

	inferred  72 D-type flip-flop(s).
Unit <opb_ipif_slv_ps2_reg_dual> synthesized.


Synthesizing Unit <ps2_sie>.
    Related source file is "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2_sie.v".
    Found finite state machine <FSM_0> for signal <detect_clk_cs>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | Rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <rx_ctl_cs>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | $or0000 (positive)                             |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <tx_ctl_cs>.
    -----------------------------------------------------------------------
    | States             | 16                                             |
    | Transitions        | 32                                             |
    | Inputs             | 6                                              |
    | Outputs            | 24                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | Rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000000000000001                               |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <Txpd>.
    Found 1-bit register for signal <Clkpd>.
    Found 1-bit xor8 for signal <$xor0002> created at line 563.
    Found 1-bit xor8 for signal <$xor0006>.
    Found 1-bit xor2 for signal <$xor0007> created at line 401.
    Found 15-bit up counter for signal <bit_wdt_counter>.
    Found 1-bit register for signal <clkin_1>.
    Found 1-bit register for signal <clkin_2>.
    Found 9-bit up counter for signal <dbc_counter>.
    Found 11-bit register for signal <q>.
    Found 15-bit up counter for signal <rts_counter>.
    Found 1-bit register for signal <rx_1>.
    Found 1-bit register for signal <rx_2>.
    Found 5-bit up counter for signal <rx_bit_count>.
    Found 1-bit register for signal <rx_full_sta_dly>.
    Found 1-bit register for signal <tx_ack_set_temp>.
    Found 1-bit register for signal <tx_full_clr_temp>.
    Found 1-bit register for signal <tx_noack_set_temp>.
    Summary:
	inferred   3 Finite State Machine(s).
	inferred   4 Counter(s).
	inferred  21 D-type flip-flop(s).
	inferred   2 Xor(s).
Unit <ps2_sie> synthesized.


Synthesizing Unit <ps2_reg>.
    Related source file is "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2_reg.v".
    Found 1-bit register for signal <IP2Bus_WrAck>.
    Found 1-bit register for signal <IP2Bus_RdAck>.
    Found 1-bit register for signal <Bus2IP_RdReq_d1>.
    Found 1-bit register for signal <Bus2IP_WrReq_d1>.
    Found 8-bit register for signal <rx_data_q>.
    Found 1-bit register for signal <srst_q>.
    Found 8-bit register for signal <tx_data_q>.
    Summary:
	inferred  21 D-type flip-flop(s).
Unit <ps2_reg> synthesized.


Synthesizing Unit <ps2>.
    Related source file is "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2.v".
Unit <ps2> synthesized.


Synthesizing Unit <opb_ps2_dual_ref>.
    Related source file is "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/opb_ps2_dual_ref.v".
WARNING:Xst:646 - Signal <Bus2IP_Addr<0:18>> is assigned but never used.
WARNING:Xst:646 - Signal <Bus2IP_Addr<20:31>> is assigned but never used.
WARNING:Xst:1780 - Signal <IP2Bus_Intr> is never used or assigned.
Unit <opb_ps2_dual_ref> synthesized.


Synthesizing Unit <ps2_ports_wrapper>.
    Related source file is "../hdl/ps2_ports_wrapper.v".
Unit <ps2_ports_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 6
 15-bit up counter                                     : 2
 5-bit up counter                                      : 2
 9-bit up counter                                      : 2
# Registers                                            : 63
 1-bit register                                        : 54
 11-bit register                                       : 2
 32-bit register                                       : 1
 8-bit register                                        : 6
# Xors                                                 : 6
 1-bit xor2                                            : 2
 1-bit xor8                                            : 4

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <ps2_ports/ps2_I1/ps2_sie_I/tx_ctl_cs> on signal <tx_ctl_cs[1:4]> with gray encoding.
------------------------------
 State            | Encoding
------------------------------
 0000000000000001 | 0000
 0000000000000010 | 0001
 0000000000000100 | 0011
 0000000000001000 | 0010
 0000000000010000 | 0110
 0000000000100000 | 0111
 0000000001000000 | 0101
 0000000010000000 | 0100
 0000000100000000 | 1100
 0000001000000000 | 1101
 0000010000000000 | 1111
 0000100000000000 | 1110
 0001000000000000 | 1010
 0010000000000000 | 1011
 0100000000000000 | 1001
 1000000000000000 | 1000
------------------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <ps2_ports/ps2_I1/ps2_sie_I/rx_ctl_cs> on signal <rx_ctl_cs[1:3]> with sequential encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 000
 000010 | 001
 000100 | 010
 001000 | 011
 010000 | 100
 100000 | 101
--------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <ps2_ports/ps2_I1/ps2_sie_I/detect_clk_cs> on signal <detect_clk_cs[1:3]> with gray encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 000
 000010 | 001
 000100 | 011
 001000 | 010
 010000 | 110
 100000 | 111
--------------------
Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 3
# Counters                                             : 6
 15-bit up counter                                     : 2
 5-bit up counter                                      : 2
 9-bit up counter                                      : 2
# Registers                                            : 138
 Flip-Flops                                            : 138
# Xors                                                 : 6
 1-bit xor2                                            : 2
 1-bit xor8                                            : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ps2_ports_wrapper> ...

Optimizing unit <ps2_sie> ...

Optimizing unit <opb_ps2_dual_ref> ...

Optimizing unit <opb_ipif_slv_ps2_reg_dual> ...

Optimizing unit <ps2_reg> ...

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <ps2_ports/IPIF/ip_retry_req> (without init value) has a constant value of 0 in block <ps2_ports_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <ps2_ports/IPIF/ip_tout_sup_req> (without init value) has a constant value of 0 in block <ps2_ports_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <ps2_ports/IPIF/Sl_errAck> (without init value) has a constant value of 0 in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_31> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_30> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_29> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_28> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_27> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_26> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_25> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_24> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_23> is unconnected in block <ps2_ports_wrapper>.
WARNING:Xst:1291 - FF/Latch <ps2_ports/IPIF/Bus2IP_Addr_22> is unconnected in block <ps2_ports_wrapper>.