ps2_ports_wrapper_xst.srp

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Release 8.2.02i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "ps2_ports_wrapper_xst.prj"
Verilog Include Directory          : {"C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a\hdl\verilog\" }

---- Target Parameters
Target Device                      : xc2vp30ff896-7
Output File Name                   : "../implementation/ps2_ports_wrapper.ngc"

---- Source Options
Top Module Name                    : ps2_ports_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2_sie.v" in library opb_ps2_dual_ref_v1_00_a
Compiling verilog file "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2_reg.v" in library opb_ps2_dual_ref_v1_00_a
Module <ps2_sie> compiled
Compiling verilog file "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2.v" in library opb_ps2_dual_ref_v1_00_a
Module <ps2_reg> compiled
Compiling verilog file "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/opb_ipif_slv_ps2_reg_dual.v" in library opb_ps2_dual_ref_v1_00_a
Module <ps2> compiled
Compiling verilog file "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/opb_ps2_dual_ref.v" in library opb_ps2_dual_ref_v1_00_a
Module <opb_ipif_slv_ps2_reg_dual> compiled
Module <opb_ps2_dual_ref> compiled
Compiling verilog file "../hdl/ps2_ports_wrapper.v" in library work
Module <ps2_ports_wrapper> compiled
No errors in compilation
Analysis of file <"ps2_ports_wrapper_xst.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <ps2_ports_wrapper> in library <work>.

Analyzing hierarchy for module <opb_ps2_dual_ref> in library <opb_ps2_dual_ref_v1_00_a> with parameters.
	C_BASEADDR = "01111010010000000000000000000000"
	C_HIGHADDR = "01111010010000001111111111111111"

Analyzing hierarchy for module <ps2> in library <opb_ps2_dual_ref_v1_00_a>.

Analyzing hierarchy for module <opb_ipif_slv_ps2_reg_dual> in library <opb_ps2_dual_ref_v1_00_a> with parameters.
	C_PS2_BAR = "01111010010000000000000000000000"

Analyzing hierarchy for module <ps2_sie> in library <opb_ps2_dual_ref_v1_00_a> with parameters.
	BIT_WDT_TMR_BITS = "00000000000000000000000000001111"
	BIT_WDT_TMR_VALUE = "00000000000000001001110001000000"
	DBC_TMR_BITS = "00000000000000000000000000001001"
	DBC_TMR_VALUE = "00000000000000000000000101110010"
	DETECT_CLK_FALL = "000010"
	DETECT_CLK_FDBC = "000100"
	DETECT_CLK_HIGH = "000001"
	DETECT_CLK_LOW = "001000"
	DETECT_CLK_RDBC = "100000"
	DETECT_CLK_RISE = "010000"
	REQ_SND_BITS = "00000000000000000000000000001111"
	REQ_SND_VALUE = "00000000000000000010011100010000"
	RX_CTL_CHECKB1 = "001000"
	RX_CTL_ERR1 = "010000"
	RX_CTL_GETB1 = "000100"
	RX_CTL_IDLE = "000001"
	RX_CTL_STARTCNT = "000010"
	RX_CTL_USEB1 = "100000"
	TX_CTL_CHKACK = "1000000000000000"
	TX_CTL_CLKPD = "0000000000000100"
	TX_CTL_DATAPD = "0000000000001000"
	TX_CTL_IDLE = "0000000000000001"
	TX_CTL_PRTY = "0001000000000000"
	TX_CTL_SND0 = "0000100000000000"
	TX_CTL_SND1 = "0000010000000000"
	TX_CTL_SND2 = "0000001000000000"
	TX_CTL_SND3 = "0000000100000000"
	TX_CTL_SND4 = "0000000010000000"
	TX_CTL_SND5 = "0000000001000000"
	TX_CTL_SND6 = "0000000000100000"
	TX_CTL_SND7 = "0000000000010000"
	TX_CTL_STOP = "0010000000000000"
	TX_CTL_WAIT = "0000000000000010"
	TX_CTL_WAITFEDGE = "0100000000000000"

Analyzing hierarchy for module <ps2_reg> in library <opb_ps2_dual_ref_v1_00_a>.

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <ps2_ports_wrapper>.
Module <ps2_ports_wrapper> is correct for synthesis.
 
    Set user-defined property "X_CORE_INFO =  opb_ps2_dual_ref_v1_00_a" for unit <ps2_ports_wrapper>.
Analyzing module <opb_ps2_dual_ref> in library <opb_ps2_dual_ref_v1_00_a>.
	C_BASEADDR = 32'b01111010010000000000000000000000
	C_HIGHADDR = 32'b01111010010000001111111111111111
Module <opb_ps2_dual_ref> is correct for synthesis.
 
Analyzing module <ps2> in library <opb_ps2_dual_ref_v1_00_a>.
Module <ps2> is correct for synthesis.
 
Analyzing module <ps2_sie> in library <opb_ps2_dual_ref_v1_00_a>.
	BIT_WDT_TMR_VALUE = 32'sb00000000000000001001110001000000
	BIT_WDT_TMR_BITS = 32'sb00000000000000000000000000001111
	DBC_TMR_VALUE = 32'sb00000000000000000000000101110010
	DBC_TMR_BITS = 32'sb00000000000000000000000000001001
	REQ_SND_VALUE = 32'sb00000000000000000010011100010000
	REQ_SND_BITS = 32'sb00000000000000000000000000001111
	DETECT_CLK_HIGH = 6'b000001
	DETECT_CLK_FALL = 6'b000010
	DETECT_CLK_FDBC = 6'b000100
	DETECT_CLK_LOW = 6'b001000
	DETECT_CLK_RISE = 6'b010000
	DETECT_CLK_RDBC = 6'b100000
	RX_CTL_IDLE = 6'b000001
	RX_CTL_STARTCNT = 6'b000010
	RX_CTL_GETB1 = 6'b000100
	RX_CTL_CHECKB1 = 6'b001000
	RX_CTL_ERR1 = 6'b010000
	RX_CTL_USEB1 = 6'b100000
	TX_CTL_IDLE = 16'b0000000000000001
	TX_CTL_WAIT = 16'b0000000000000010
	TX_CTL_CLKPD = 16'b0000000000000100
	TX_CTL_DATAPD = 16'b0000000000001000
	TX_CTL_SND7 = 16'b0000000000010000
	TX_CTL_SND6 = 16'b0000000000100000
	TX_CTL_SND5 = 16'b0000000001000000
	TX_CTL_SND4 = 16'b0000000010000000
	TX_CTL_SND3 = 16'b0000000100000000
	TX_CTL_SND2 = 16'b0000001000000000
	TX_CTL_SND1 = 16'b0000010000000000
	TX_CTL_SND0 = 16'b0000100000000000
	TX_CTL_PRTY = 16'b0001000000000000
	TX_CTL_STOP = 16'b0010000000000000
	TX_CTL_WAITFEDGE = 16'b0100000000000000
	TX_CTL_CHKACK = 16'b1000000000000000
Module <ps2_sie> is correct for synthesis.
 
Analyzing module <ps2_reg> in library <opb_ps2_dual_ref_v1_00_a>.
Module <ps2_reg> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <tx_data_fl_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <rx_data_fl_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <int_rx_full_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <int_rx_err_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <int_rx_ovf_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <int_tx_ack_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <int_tx_noack_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <int_wdt_tout_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <intm_rx_full_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <intm_rx_err_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <intm_rx_ovf_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <intm_tx_ack_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <intm_tx_noack_reg> in unit <ps2_reg>.
    Set user-defined property "INIT =  0" for instance <intm_wdt_tout_reg> in unit <ps2_reg>.
Analyzing module <opb_ipif_slv_ps2_reg_dual> in library <opb_ps2_dual_ref_v1_00_a>.
	C_PS2_BAR = 32'b01111010010000000000000000000000
Module <opb_ipif_slv_ps2_reg_dual> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <opb_ipif_slv_ps2_reg_dual>.
    Related source file is "C:\V2P_CD\V2P_CD\lib\lib_rev_1_1\lib\XilinxProcessorIP\pcores\opb_ps2_dual_ref_v1_00_a/hdl/verilog/opb_ipif_slv_ps2_reg_dual.v".
WARNING:Xst:647 - Input <OPB_DBus<8:31>> is never used.
WARNING:Xst:647 - Input <OPB_seqAddr> is never used.
WARNING:Xst:646 - Signal <Bus2IP_BE> is assigned but never used.
    Found 16-bit register for signal <Bus2IP_RegCE>.
    Found 8-bit register for signal <Bus2IP_Data>.
    Found 32-bit register for signal <Bus2IP_Addr>.
    Found 1-bit register for signal <Sl_errAck>.
    Found 1-bit register for signal <addr_hit>.
    Found 1-bit register for signal <gen_xfer_ack>.
    Found 1-bit register for signal <ip_retry_req>.
    Found 1-bit register for signal <ip_tout_sup_req>.
    Found 1-bit register for signal <opb_req_clr>.
    Found 1-bit register for signal <opb_rnw_d1>.
    Found 1-bit register for signal <reg_ce_d1>.
    Found 8-bit register for signal <Sl_DBus_int>.
    Summary: