plb_wrapper_xst.prj

本系统由服务器软件控制平台和fpga硬件处理系统组成

VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/pselect.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/down_counter.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_bits.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_gate.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/arb_addr_sel.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/arb_control_sm.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/bus_control.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/arb_registers.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/bus_lock_sm.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/dcr_regs.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/gen_qual_req.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/muxed_signals.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/pend_request.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/qual_priority.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/pending_priority.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/qual_request.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/priority_encoder.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/plb_priority_encoder.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/watchdog_timer.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/plb_wr_datapath.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/plb_rd_datapath.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/plb_addrpath.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/plb_slave_ors.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/plb_interrupt.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/plb_arbiter_logic.vhd
VHDL plb_v34_v1_02_a g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v34_v1_02_a/hdl/vhdl/plb_v34.vhd
vhdl work ../hdl/plb_wrapper.vhd