reset_block_wrapper_xst.srp

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HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 4-bit up counter                                      : 1
 6-bit up counter                                      : 1
# Registers                                            : 48
 1-bit register                                        : 48

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 4-bit up counter                                      : 1
 6-bit up counter                                      : 1
# Registers                                            : 48
 Flip-Flops                                            : 48

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <reset_block_wrapper> ...

Optimizing unit <sequence> ...

Optimizing unit <lpf> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

Processing Unit <reset_block_wrapper> :
	Found 2-bit shift register for signal <reset_block/Core_Reset_Req_d2>.
	Found 2-bit shift register for signal <reset_block/SEQ/system_Reset_Req_d2>.
	Found 2-bit shift register for signal <reset_block/SEQ/chip_Reset_Req_d2>.
	Found 2-bit shift register for signal <reset_block/EXT_LPF/asr_lpf_0>.
Unit <reset_block_wrapper> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 50
 Flip-Flops                                            : 50
# Shift Registers                                      : 4
 2-bit shift register                                  : 4

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/reset_block_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 12

Cell Usage :
# BELS                             : 42
#      GND                         : 1
#      INV                         : 5
#      LUT2                        : 12
#      LUT3                        : 6
#      LUT3_D                      : 1
#      LUT4                        : 16
#      VCC                         : 1
# FlipFlops/Latches                : 54
#      FD                          : 23
#      FDR                         : 11
#      FDRE                        : 10
#      FDS                         : 3
#      FDSE                        : 7
# Shift Registers                  : 5
#      SRL16                       : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                      31  out of  13696     0%  
 Number of Slice Flip Flops:            54  out of  27392     0%  
 Number of 4 input LUTs:                45  out of  27392     0%  
    Number used as logic:               40
    Number used as Shift registers:      5
 Number of IOs:                         12
 Number of bonded IOBs:                  0  out of    556     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                    | Load  |
-----------------------------------+------------------------------------------+-------+
Slowest_sync_clk                   | NONE(reset_block/SEQ/SEQ_COUNTER/q_int_0)| 59    |
-----------------------------------+------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 3.588ns (Maximum Frequency: 278.746MHz)
   Minimum input arrival time before clock: 0.581ns
   Maximum output required time after clock: 0.370ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'Slowest_sync_clk'
  Clock period: 3.588ns (frequency: 278.746MHz)
  Total number of paths / destination ports: 161 / 83
-------------------------------------------------------------------------
Delay:               3.588ns (Levels of Logic = 0)
  Source:            reset_block/EXT_LPF/POR_SRL_I (FF)
  Destination:       reset_block/EXT_LPF/lpf_int (FF)
  Source Clock:      Slowest_sync_clk rising
  Destination Clock: Slowest_sync_clk rising

  Data Path: reset_block/EXT_LPF/POR_SRL_I to reset_block/EXT_LPF/lpf_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16:CLK->Q          1   2.720   0.331  reset_block/EXT_LPF/POR_SRL_I (reset_block/EXT_LPF/srl_time_out)
     FDS:S                     0.536          reset_block/EXT_LPF/lpf_int
    ----------------------------------------
    Total                      3.588ns (3.256ns logic, 0.331ns route)
                                       (90.8% logic, 9.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Slowest_sync_clk'
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset:              0.581ns (Levels of Logic = 1)
  Source:            Dcm_locked (PAD)
  Destination:       reset_block/EXT_LPF/lpf_int (FF)
  Destination Clock: Slowest_sync_clk rising

  Data Path: Dcm_locked to reset_block/EXT_LPF/lpf_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I1->O            1   0.275   0.000  reset_block/EXT_LPF/_or0000111 (N44)
     FDS:D                     0.208          reset_block/EXT_LPF/lpf_int
    ----------------------------------------
    Total                      0.581ns (0.581ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Slowest_sync_clk'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              0.370ns (Levels of Logic = 0)
  Source:            reset_block/Rstc405resetchip (FF)
  Destination:       Rstc405resetchip (PAD)
  Source Clock:      Slowest_sync_clk rising

  Data Path: reset_block/Rstc405resetchip to Rstc405resetchip
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               0   0.370   0.000  reset_block/Rstc405resetchip (Rstc405resetchip)
    ----------------------------------------
    Total                      0.370ns (0.370ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 17.50 / 17.64 s | Elapsed : 17.00 / 18.00 s
 
--> 

Total memory usage is 187968 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    1 (   0 filtered)