reset_block_wrapper_xst.srp

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Release 8.2.02i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "reset_block_wrapper_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff896-7
Output File Name                   : "../implementation/reset_block_wrapper.ngc"

---- Source Options
Top Module Name                    : reset_block_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/upcnt_n.vhd" in Library proc_sys_reset_v1_00_a.
Entity <upcnt_n> compiled.
Entity <upcnt_n> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/lpf.vhd" in Library proc_sys_reset_v1_00_a.
Entity <lpf> compiled.
Entity <lpf> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/sequence.vhd" in Library proc_sys_reset_v1_00_a.
Entity <sequence> compiled.
Entity <sequence> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/proc_sys_reset.vhd" in Library proc_sys_reset_v1_00_a.
Entity <proc_sys_reset> compiled.
Entity <proc_sys_reset> (Architecture <imp>) compiled.
Compiling vhdl file "C:/myproj2/firewall/myxps/hdl/reset_block_wrapper.vhd" in Library work.
Entity <reset_block_wrapper> compiled.
Entity <reset_block_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <reset_block_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <proc_sys_reset> in library <proc_sys_reset_v1_00_a> (architecture <imp>) with generics.
	C_NUM_BUS_RST = 1
	C_AUX_RESET_HIGH = '1'
	C_AUX_RST_WIDTH = 4
	C_EXT_RESET_HIGH = '0'
	C_EXT_RST_WIDTH = 4
	C_NUM_PERP_RST = 1

Analyzing hierarchy for entity <upcnt_n> in library <proc_sys_reset_v1_00_a> (architecture <imp>) with generics.
	C_SIZE = 4

Analyzing hierarchy for entity <lpf> in library <proc_sys_reset_v1_00_a> (architecture <imp>) with generics.
	C_AUX_RESET_HIGH = '1'
	C_AUX_RST_WIDTH = 4
	C_EXT_RESET_HIGH = '0'
	C_EXT_RST_WIDTH = 4

Analyzing hierarchy for entity <sequence> in library <proc_sys_reset_v1_00_a> (architecture <imp>).

Analyzing hierarchy for entity <upcnt_n> in library <proc_sys_reset_v1_00_a> (architecture <imp>) with generics.
	C_SIZE = 6

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <reset_block_wrapper> in library <work> (Architecture <STRUCTURE>).
    Set user-defined property "X_CORE_INFO =  proc_sys_reset_v1_00_a" for unit <reset_block_wrapper>.
    Set property "equivalent_register_removal = no" for signal <Bus_Struct_Reset> in unit <proc_sys_reset>.
    Set property "equivalent_register_removal = no" for signal <Peripheral_Reset> in unit <proc_sys_reset>.
Entity <reset_block_wrapper> analyzed. Unit <reset_block_wrapper> generated.

Analyzing generic Entity <proc_sys_reset> in library <proc_sys_reset_v1_00_a> (Architecture <imp>).
	C_NUM_BUS_RST = 1
	C_NUM_PERP_RST = 1
	C_AUX_RST_WIDTH = 4
	C_AUX_RESET_HIGH = '1'
	C_EXT_RESET_HIGH = '0'
	C_EXT_RST_WIDTH = 4
Entity <proc_sys_reset> analyzed. Unit <proc_sys_reset> generated.

Analyzing generic Entity <upcnt_n.1> in library <proc_sys_reset_v1_00_a> (Architecture <imp>).
	C_SIZE = 4
Entity <upcnt_n.1> analyzed. Unit <upcnt_n.1> generated.

Analyzing generic Entity <lpf> in library <proc_sys_reset_v1_00_a> (Architecture <imp>).
	C_AUX_RESET_HIGH = '1'
	C_AUX_RST_WIDTH = 4
	C_EXT_RESET_HIGH = '0'
	C_EXT_RST_WIDTH = 4
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/lpf.vhd" line 170: Instantiating black box module <SRL16>.
    Set user-defined property "INIT =  FFFF" for instance <POR_SRL_I> in unit <lpf>.
Entity <lpf> analyzed. Unit <lpf> generated.

Analyzing Entity <sequence> in library <proc_sys_reset_v1_00_a> (Architecture <imp>).
Entity <sequence> analyzed. Unit <sequence> generated.

Analyzing generic Entity <upcnt_n.2> in library <proc_sys_reset_v1_00_a> (Architecture <imp>).
	C_SIZE = 6
Entity <upcnt_n.2> analyzed. Unit <upcnt_n.2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <upcnt_n_1>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/upcnt_n.vhd".
    Found 4-bit up counter for signal <q_int>.
    Summary:
	inferred   1 Counter(s).
Unit <upcnt_n_1> synthesized.


Synthesizing Unit <upcnt_n_2>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/upcnt_n.vhd".
    Found 6-bit up counter for signal <q_int>.
    Summary:
	inferred   1 Counter(s).
Unit <upcnt_n_2> synthesized.


Synthesizing Unit <lpf>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/lpf.vhd".
    Found 1-bit register for signal <asr_d1>.
    Found 4-bit register for signal <asr_lpf>.
    Found 1-bit register for signal <exr_d1>.
    Found 4-bit register for signal <exr_lpf>.
    Found 1-bit register for signal <lpf_asr>.
    Found 1-bit register for signal <lpf_exr>.
    Found 1-bit register for signal <lpf_int>.
    Summary:
	inferred  13 D-type flip-flop(s).
Unit <lpf> synthesized.


Synthesizing Unit <sequence>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/sequence.vhd".
WARNING:Xst:1780 - Signal <Core> is never used or assigned.
    Register <bsr_dec<1>> equivalent to <pr_dec<1>> has been removed
    Found 1-bit register for signal <bsr>.
    Found 1-bit register for signal <bsr_dec<2>>.
    Found 1-bit register for signal <bsr_dec<0>>.
    Found 1-bit register for signal <Chip>.
    Found 3-bit register for signal <chip_dec>.
    Found 1-bit register for signal <chip_Reset_Req_d1>.
    Found 1-bit register for signal <chip_Reset_Req_d2>.
    Found 1-bit register for signal <chip_Reset_Req_d3>.
    Found 1-bit register for signal <pr>.
    Found 3-bit register for signal <pr_dec>.
    Found 1-bit register for signal <ris_edge>.
    Found 1-bit register for signal <seq_clr>.
    Found 1-bit register for signal <seq_cnt_en>.
    Found 1-bit register for signal <Sys>.
    Found 3-bit register for signal <sys_dec>.
    Found 1-bit register for signal <sys_edge>.
    Found 1-bit register for signal <system_Reset_Req_d1>.
    Found 1-bit register for signal <system_Reset_Req_d2>.
    Found 1-bit register for signal <system_Reset_Req_d3>.
    Summary:
	inferred  25 D-type flip-flop(s).
Unit <sequence> synthesized.


Synthesizing Unit <proc_sys_reset>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v1_00_a/hdl/vhdl/proc_sys_reset.vhd".
    Found 1-bit register for signal <Rstc405resetchip>.
    Found 1-bit register for signal <Rstc405resetcore>.
    Found 1-bit register for signal <Peripheral_Reset<0>>.
    Found 1-bit register for signal <Bus_Struct_Reset<0>>.
    Found 1-bit register for signal <Rstc405resetsys>.
    Found 1-bit register for signal <core_cnt_en>.
    Found 1-bit register for signal <core_req_edge>.
    Found 1-bit register for signal <Core_Reset_Req_d1>.
    Found 1-bit register for signal <Core_Reset_Req_d2>.
    Found 1-bit register for signal <Core_Reset_Req_d3>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <proc_sys_reset> synthesized.


Synthesizing Unit <reset_block_wrapper>.
    Related source file is "C:/myproj2/firewall/myxps/hdl/reset_block_wrapper.vhd".
Unit <reset_block_wrapper> synthesized.


=========================================================================