plb_bram_if_cntlr_1_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_ipif.vhd" line 1962: Unconnected output port 'Sl_SSize' of component 'plb_slave_attachment_indet'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_ipif.vhd" line 1962: Unconnected output port 'Bus2IP_BE' of component 'plb_slave_attachment_indet'.
Entity <plb_ipif> analyzed. Unit <plb_ipif> generated.

Analyzing generic Entity <or_gate.1> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_OR_WIDTH = 1
	C_BUS_WIDTH = 8
	C_USE_LUT_OR = true
Entity <or_gate.1> analyzed. Unit <or_gate.1> generated.

Analyzing generic Entity <or_gate.2> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_BUS_WIDTH = 64
	C_USE_LUT_OR = true
	C_OR_WIDTH = 1
Entity <or_gate.2> analyzed. Unit <or_gate.2> generated.

Analyzing generic Entity <plb_slave_attachment_indet> in library <plb_ipif_v1_00_e> (Architecture <implementation>).
	C_ARD_DWIDTH_ARRAY = (64)
	C_ARD_NUM_CE_ARRAY = (1)
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011111111111111110000000000000000",
	                          "0000000000000000000000000000000011111111111111111111111111111111")
	C_IPIF_ABUS_WIDTH = 32
	C_FAST_DATA_XFER = false
	C_DPHASE_TIMEOUT = 64
	C_MA2SA_NUM_WIDTH = 4
	C_IPIF_DBUS_WIDTH = 64
	C_BURST_PAGE_SIZE = 1024
	C_PLB_ABUS_WIDTH = 32
	C_PLB_DBUS_WIDTH = 64
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SL_ATT_ADDR_SEL_WIDTH = 2
	C_SLN_BUFFER_DEPTH = 8
	C_STEER_ADDR_SIZE = 10
	C_SUPPORT_BURST = true
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_slave_attachment_indet.vhd" line 1604: Unconnected output port 'Count_Out' of component 'Counter'.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
Entity <plb_slave_attachment_indet> analyzed. Unit <plb_slave_attachment_indet> generated.

Analyzing generic Entity <plb_address_decoder> in library <plb_ipif_v1_00_e> (Architecture <IMP>).
	C_BUS_AWIDTH = 32
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011111111111111110000000000000000",
	                          "0000000000000000000000000000000011111111111111111111111111111111")
	C_ARD_DWIDTH_ARRAY = (64)
	C_ARD_NUM_CE_ARRAY = (1)
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 488: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 488: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 488: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 502: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 540: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 552: Instantiating black box module <FDRE>.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 724: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 736: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 748: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 766: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 778: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 787: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd" line 796: Instantiating black box module <FDRE>.
Entity <plb_address_decoder> analyzed. Unit <plb_address_decoder> generated.

Analyzing generic Entity <pselect> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_BAR = "11111111111111110000000000000000"
	C_AW = 32
	C_AB = 16
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect> analyzed. Unit <pselect> generated.

Analyzing generic Entity <or_gate.3> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_BUS_WIDTH = 3
	C_OR_WIDTH = 1
	C_USE_LUT_OR = true
Entity <or_gate.3> analyzed. Unit <or_gate.3> generated.

Analyzing generic Entity <or_gate.4> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = true
Entity <or_gate.4> analyzed. Unit <or_gate.4> generated.

Analyzing generic Entity <Counter> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_NUM_BITS = 7
    Set user-defined property "INIT =  0" for instance <CARRY_OUT_I> in unit <Counter>.
Entity <Counter> analyzed. Unit <Counter> generated.

Analyzing Entity <counter_bit> in library <proc_common_v1_00_b> (Architecture <imp>).
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/counter_bit.vhd" line 126: Instantiating black box module <LUT4>.
    Set user-defined property "INIT =  36C6" for instance <I_ALU_LUT> in unit <counter_bit>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/counter_bit.vhd" line 137: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/counter_bit.vhd" line 144: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/counter_bit.vhd" line 150: Instantiating black box module <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit> generated.

Analyzing generic Entity <addr_reg_cntr_brst_flex> in library <plb_ipif_v1_00_e> (Architecture <implementation>).
	C_NUM_ADDR_BITS = 32
	C_PLB_DWIDTH = 64
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 250: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 259: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 269: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 294: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 294: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 294: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 294: Instantiating black box module <FDRE>.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 363: Unconnected output port 'Carry_Out' of component 'flex_addr_cntr'.
Entity <addr_reg_cntr_brst_flex> analyzed. Unit <addr_reg_cntr_brst_flex> generated.

Analyzing generic Entity <flex_addr_cntr> in library <plb_ipif_v1_00_e> (Architecture <implementation>).
	C_AWIDTH = 32
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 249: Instantiating black box module <LUT4>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[7].I_LUT_N> in unit <flex_addr_cntr>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 261: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 269: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 276: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 249: Instantiating black box module <LUT4>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[8].I_LUT_N> in unit <flex_addr_cntr>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 261: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 269: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 276: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 249: Instantiating black box module <LUT4>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[9].I_LUT_N> in unit <flex_addr_cntr>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 261: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 269: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 276: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 249: Instantiating black box module <LUT4>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[10].I_LUT_N> in unit <flex_addr_cntr>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 261: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 269: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 276: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 249: Instantiating black box module <LUT4>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[11].I_LUT_N> in unit <flex_addr_cntr>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 261: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 269: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 276: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd" line 249: Instantiating black box module <LUT4>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[12].I_LUT_N> in unit <flex_addr_cntr>.