plb_bram_if_cntlr_1_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

	C_NUM_ADDR_BITS = 32
	C_PLB_DWIDTH = 64

Analyzing hierarchy for entity <pselect> in library <proc_common_v1_00_b> (architecture <imp>) with generics.
	C_BAR = "11111111111111110000000000000000"
	C_AW = 32
	C_AB = 16

Analyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics.
	C_USE_LUT_OR = true
	C_OR_WIDTH = 1
	C_BUS_WIDTH = 3

Analyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics.
	C_USE_LUT_OR = true
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1

Analyzing hierarchy for entity <counter_bit> in library <proc_common_v1_00_b> (architecture <imp>).

Analyzing hierarchy for entity <flex_addr_cntr> in library <plb_ipif_v1_00_e> (architecture <implementation>) with generics.
	C_AWIDTH = 32

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <plb_bram_if_cntlr_1_wrapper> in library <work> (Architecture <STRUCTURE>).
    Set user-defined property "X_CORE_INFO =  plb_bram_if_cntlr_v1_00_b" for unit <plb_bram_if_cntlr_1_wrapper>.
WARNING:Xst:37 - Unknown property "SPECIAL".
WARNING:Xst:37 - Unknown property "ADDR_SLICE".
WARNING:Xst:37 - Unknown property "NUM_WRITE_ENABLES".
WARNING:Xst:37 - Unknown property "AWIDTH".
WARNING:Xst:37 - Unknown property "DWIDTH".
    Set property "MAX_FANOUT = 10000" for signal <PLB_Clk> in unit <plb_bram_if_cntlr>.
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <PLB_Rst> in unit <plb_bram_if_cntlr>.
WARNING:Xst:37 - Unknown property "SIGIS".
WARNING:Xst:37 - Unknown property "ADDR_SLICE".
WARNING:Xst:37 - Unknown property "AWIDTH".
WARNING:Xst:37 - Unknown property "DWIDTH".
WARNING:Xst:37 - Unknown property "NUM_WRITE_ENABLES".
WARNING:Xst:37 - Unknown property "SPECIAL".
Entity <plb_bram_if_cntlr_1_wrapper> analyzed. Unit <plb_bram_if_cntlr_1_wrapper> generated.

Analyzing generic Entity <plb_bram_if_cntlr> in library <plb_bram_if_cntlr_v1_00_b> (Architecture <implementation>).
	c_plb_clk_period_ps = 10000
	c_num_masters = 2
	c_plb_awidth = 32
	c_plb_dwidth = 64
	c_plb_mid_width = 1
	c_baseaddr = "11111111111111110000000000000000"
	c_highaddr = "11111111111111111111111111111111"
	c_include_burst_cacheln_support = 0
WARNING:Xst:37 - Unknown property "SIGIS".
WARNING:Xst:37 - Unknown property "SIGIS".
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'IP2INTC_Irpt' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_request' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_priority' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_buslock' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_RNW' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_BE' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_MSize' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_size' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_type' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_compress' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_guarded' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_ordered' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_lockErr' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_abort' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_ABus' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_wrDBus' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_wrBurst' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'M_rdBurst' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_Clk' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_Reset' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_Freeze' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_Burst' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_IBurst' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_RNW_Early' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_PselHit' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_CE' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_RdCE' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_WrCE' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_MstWrAck' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_MstRdAck' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_MstRetry' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_MstError' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_MstTimeOut' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_MstLastAck' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'RFIFO2IP_WrAck' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'RFIFO2IP_AlmostFull' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'RFIFO2IP_Full' of component 'plb_ipif'.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'RFIFO2IP_Vacancy' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'WFIFO2IP_Data' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'WFIFO2IP_RdAck' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'WFIFO2IP_AlmostEmpty' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'WFIFO2IP_Empty' of component 'plb_ipif'.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'WFIFO2IP_Occupancy' of component 'plb_ipif'.
WARNING:Xst:753 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" line 387: Unconnected output port 'Bus2IP_DMA_Ack' of component 'plb_ipif'.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
Entity <plb_bram_if_cntlr> analyzed. Unit <plb_bram_if_cntlr> generated.

Analyzing generic Entity <plb_ipif> in library <plb_ipif_v1_00_e> (Architecture <implementation>).
	C_IP_INTR_MODE_ARRAY = (0,0)
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011111111111111110000000000000000",
	                          "0000000000000000000000000000000011111111111111111111111111111111")
	C_DEV_DPHASE_TIMEOUT = 64
	C_DEV_BURST_ENABLE = true
	C_DEV_FAST_DATA_XFER = false
	C_ARD_NUM_CE_ARRAY = (1)
	C_DEV_MIR_ENABLE = false
	C_FAMILY = "virtex2p"
	C_DEV_MAX_BURST_SIZE = 64
	C_ARD_ID_ARRAY = (120)
	C_ARD_DWIDTH_ARRAY = (64)
	C_DEV_BURST_PAGE_SIZE = 1024
	C_DEV_BLK_ID = 0
	C_WRFIFO_DEPTH = 512
	C_IPIF_AWIDTH = 32
	C_WRFIFO_INCLUDE_VACANCY = true
	C_RDFIFO_DEPTH = 512
	C_INCLUDE_DEV_ISC = false
	C_INCLUDE_DEV_PENCODER = false
	C_WRFIFO_INCLUDE_PACKET_MODE = false
	C_IP_MASTER_PRESENT = false
	C_RDFIFO_INCLUDE_VACANCY = true
	C_PLB_NUM_MASTERS = 2
	C_PLB_DWIDTH = 64
	C_PLB_MID_WIDTH = 1
	C_IPIF_DWIDTH = 64
	C_PLB_AWIDTH = 32
	C_PLB_CLK_PERIOD_PS = 10000
	C_RDFIFO_INCLUDE_PACKET_MODE = false
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.