plb_bram_if_cntlr_1_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

Entity <burst_support> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" in Library plb_ipif_v1_00_e.
Entity <addr_reg_cntr_brst_flex> compiled.
Entity <addr_reg_cntr_brst_flex> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_slave_attachment_indet.vhd" in Library plb_ipif_v1_00_e.
Entity <plb_slave_attachment_indet> compiled.
Entity <plb_slave_attachment_indet> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_ipif_reset.vhd" in Library plb_ipif_v1_00_e.
Entity <plb_ipif_reset> compiled.
Entity <plb_ipif_reset> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_interrupt_control.vhd" in Library plb_ipif_v1_00_e.
Entity <plb_interrupt_control> compiled.
Entity <plb_interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_sesr_sear.vhd" in Library plb_ipif_v1_00_e.
Entity <plb_sesr_sear> compiled.
Entity <plb_sesr_sear> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/rdpfifo_top.vhd" in Library plb_ipif_v1_00_e.
Entity <rdpfifo_top> compiled.
Entity <rdpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/wrpfifo_top.vhd" in Library plb_ipif_v1_00_e.
Entity <wrpfifo_top> compiled.
Entity <wrpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_ipif_v1_00_e/hdl/vhdl/plb_ipif.vhd" in Library plb_ipif_v1_00_e.
Entity <plb_ipif> compiled.
Entity <plb_ipif> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_b/hdl/vhdl/bram_if.vhd" in Library bram_if_cntlr_v1_00_b.
Entity <bram_if> compiled.
Entity <bram_if> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd" in Library plb_bram_if_cntlr_v1_00_b.
Entity <plb_bram_if_cntlr> compiled.
Entity <plb_bram_if_cntlr> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/myproj2/firewall/myxps/hdl/plb_bram_if_cntlr_1_wrapper.vhd" in Library work.
Entity <plb_bram_if_cntlr_1_wrapper> compiled.
Entity <plb_bram_if_cntlr_1_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <plb_bram_if_cntlr_1_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <plb_bram_if_cntlr> in library <plb_bram_if_cntlr_v1_00_b> (architecture <implementation>) with generics.
	c_baseaddr = "11111111111111110000000000000000"
	c_highaddr = "11111111111111111111111111111111"
	c_include_burst_cacheln_support = 0
	c_num_masters = 2
	c_plb_awidth = 32
	c_plb_clk_period_ps = 10000
	c_plb_dwidth = 64
	c_plb_mid_width = 1
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.

Analyzing hierarchy for entity <plb_ipif> in library <plb_ipif_v1_00_e> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011111111111111110000000000000000",
	                          "0000000000000000000000000000000011111111111111111111111111111111")
	C_ARD_DWIDTH_ARRAY = (64)
	C_ARD_ID_ARRAY = (120)
	C_ARD_NUM_CE_ARRAY = (1)
	C_DEV_BLK_ID = 0
	C_DEV_BURST_ENABLE = true
	C_DEV_BURST_PAGE_SIZE = 1024
	C_DEV_DPHASE_TIMEOUT = 64
	C_DEV_FAST_DATA_XFER = false
	C_DEV_MAX_BURST_SIZE = 64
	C_DEV_MIR_ENABLE = false
	C_FAMILY = "virtex2p"
	C_INCLUDE_DEV_ISC = false
	C_INCLUDE_DEV_PENCODER = false
	C_IP_INTR_MODE_ARRAY = (0,0)
	C_IP_MASTER_PRESENT = false
	C_IPIF_AWIDTH = 32
	C_IPIF_DWIDTH = 64
	C_PLB_AWIDTH = 32
	C_PLB_CLK_PERIOD_PS = 10000
	C_PLB_DWIDTH = 64
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_RDFIFO_DEPTH = 512
	C_RDFIFO_INCLUDE_PACKET_MODE = false
	C_RDFIFO_INCLUDE_VACANCY = true
	C_WRFIFO_DEPTH = 512
	C_WRFIFO_INCLUDE_PACKET_MODE = false
	C_WRFIFO_INCLUDE_VACANCY = true
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.

Analyzing hierarchy for entity <bram_if> in library <bram_if_cntlr_v1_00_b> (architecture <implementation>) with generics.
	C_IPIF_DWIDTH = 64
	C_IPIF_AWIDTH = 32

Analyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics.
	C_USE_LUT_OR = true
	C_OR_WIDTH = 1
	C_BUS_WIDTH = 8

Analyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics.
	C_OR_WIDTH = 1
	C_USE_LUT_OR = true
	C_BUS_WIDTH = 64

Analyzing hierarchy for entity <plb_slave_attachment_indet> in library <plb_ipif_v1_00_e> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011111111111111110000000000000000",
	                          "0000000000000000000000000000000011111111111111111111111111111111")
	C_ARD_DWIDTH_ARRAY = (64)
	C_ARD_NUM_CE_ARRAY = (1)
	C_BURST_PAGE_SIZE = 1024
	C_DPHASE_TIMEOUT = 64
	C_FAST_DATA_XFER = false
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 64
	C_MA2SA_NUM_WIDTH = 4
	C_PLB_ABUS_WIDTH = 32
	C_PLB_DBUS_WIDTH = 64
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SL_ATT_ADDR_SEL_WIDTH = 2
	C_SLN_BUFFER_DEPTH = 8
	C_STEER_ADDR_SIZE = 10
	C_SUPPORT_BURST = true
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.

Analyzing hierarchy for entity <ipif_steer> in library <ipif_common_v1_00_b> (architecture <IMP>) with generics.
	C_AWIDTH = 32
	C_SMALLEST = 64
	C_DWIDTH = 64

Analyzing hierarchy for entity <plb_address_decoder> in library <plb_ipif_v1_00_e> (architecture <IMP>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011111111111111110000000000000000",
	                          "0000000000000000000000000000000011111111111111111111111111111111")
	C_ARD_DWIDTH_ARRAY = (64)
	C_ARD_NUM_CE_ARRAY = (1)
	C_BUS_AWIDTH = 32
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.

Analyzing hierarchy for entity <Counter> in library <proc_common_v1_00_b> (architecture <imp>) with generics.
	C_NUM_BITS = 7

Analyzing hierarchy for entity <addr_reg_cntr_brst_flex> in library <plb_ipif_v1_00_e> (architecture <implementation>) with generics.