rs232_uart_1_wrapper_xst.srp

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Unit <rs232_uart_1_wrapper> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 64
 Flip-Flops                                            : 64

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/rs232_uart_1_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 112

Cell Usage :
# BELS                             : 110
#      GND                         : 1
#      INV                         : 6
#      LUT2                        : 6
#      LUT3                        : 16
#      LUT4                        : 46
#      LUT4_D                      : 7
#      LUT4_L                      : 1
#      MUXCY                       : 4
#      MUXCY_L                     : 8
#      MUXF5                       : 2
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 11
# FlipFlops/Latches                : 64
#      FDC                         : 11
#      FDCE                        : 5
#      FDP                         : 5
#      FDPE                        : 3
#      FDR                         : 8
#      FDRE                        : 27
#      FDS                         : 4
#      FDSE                        : 1
# Shift Registers                  : 19
#      SRL16E                      : 19
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                      53  out of  13696     0%  
 Number of Slice Flip Flops:            64  out of  27392     0%  
 Number of 4 input LUTs:               101  out of  27392     0%  
    Number used as logic:               82
    Number used as Shift registers:     19
 Number of IOs:                        112
 Number of bonded IOBs:                  0  out of    556     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+-----------------------------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                                   | Load  |
-----------------------------------+-----------------------------------------------------------------------------------------+-------+
OPB_Clk                            | NONE(rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/FIFO_RAM[1].SRL16E_I)| 83    |
-----------------------------------+-----------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-------+
Control Signal                                                                                  | Buffer(FF name)                                                                  | Load  |
------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-------+
OPB_Rst                                                                                         | NONE                                                                             | 22    |
rs232_uart_1/OPB_UARTLITE_Core_I/reset_RX_FIFO(rs232_uart_1/OPB_UARTLITE_Core_I/reset_RX_FIFO:Q)| NONE(rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/SRL_FIFO_I/data_Exists_I)| 1     |
rs232_uart_1/OPB_UARTLITE_Core_I/reset_TX_FIFO(rs232_uart_1/OPB_UARTLITE_Core_I/reset_TX_FIFO:Q)| NONE(rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/data_Exists_I)| 1     |
------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 4.224ns (Maximum Frequency: 236.770MHz)
   Minimum input arrival time before clock: 2.693ns
   Maximum output required time after clock: 0.370ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'OPB_Clk'
  Clock period: 4.224ns (frequency: 236.770MHz)
  Total number of paths / destination ports: 812 / 228
-------------------------------------------------------------------------
Delay:               4.224ns (Levels of Logic = 3)
  Source:            rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[0].SRL16E_I (FF)
  Destination:       rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/serial_Data (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[0].SRL16E_I to rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/serial_Data
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16E:CLK->Q         1   2.720   0.429  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FIFO_RAM[0].SRL16E_I (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/fifo_DOut<0>)
     LUT3:I1->O            1   0.275   0.000  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/mux_011 (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/mux_01)
     MUXF5:I0->O           1   0.303   0.000  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/MUX_F5_1 (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/mux_0123)
     MUXF6:I0->O           1   0.288   0.000  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/MUXF6_I (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/mux_Out)
     FDC:D                     0.208          rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/serial_Data
    ----------------------------------------
    Total                      4.224ns (3.794ns logic, 0.429ns route)
                                       (89.8% logic, 10.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
  Total number of paths / destination ports: 150 / 52
-------------------------------------------------------------------------
Offset:              2.693ns (Levels of Logic = 6)
  Source:            OPB_ABus<29> (PAD)
  Destination:       rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[3].FDRE_I (FF)
  Destination Clock: OPB_Clk rising

  Data Path: OPB_ABus<29> to rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[3].FDRE_I
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I0->O            7   0.275   0.483  rs232_uart_1/OPB_UARTLITE_Core_I/write_TX_FIFO1 (rs232_uart_1/OPB_UARTLITE_Core_I/write_TX_FIFO)
     LUT3:I2->O            9   0.275   0.499  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/valid_Write1 (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/valid_Write)
     MUXCY_L:CI->LO        1   0.036   0.000  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[0].Used_MuxCY.MUXCY_L_I (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/addr_cy<1>)
     MUXCY_L:CI->LO        1   0.036   0.000  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[1].Used_MuxCY.MUXCY_L_I (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/addr_cy<2>)
     MUXCY_L:CI->LO        0   0.036   0.000  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[2].Used_MuxCY.MUXCY_L_I (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/addr_cy<3>)
     XORCY:CI->O           1   0.708   0.000  rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[3].XORCY_I (rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/sum_A<3>)
     FDRE:D                    0.208          rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/Addr_Counters[3].FDRE_I
    ----------------------------------------
    Total                      2.693ns (1.711ns logic, 0.982ns route)
                                       (63.5% logic, 36.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              0.370ns (Levels of Logic = 0)
  Source:            rs232_uart_1/OPB_UARTLITE_Core_I/Interrupt (FF)
  Destination:       Interrupt (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: rs232_uart_1/OPB_UARTLITE_Core_I/Interrupt to Interrupt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              0   0.370   0.000  rs232_uart_1/OPB_UARTLITE_Core_I/Interrupt (Interrupt)
    ----------------------------------------
    Total                      0.370ns (0.370ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 37.77 / 38.06 s | Elapsed : 38.00 / 38.00 s
 
--> 

Total memory usage is 188992 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   69 (   0 filtered)
Number of infos    :    2 (   0 filtered)