rs232_uart_1_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

	C_DEPTH = 16
	C_DATA_BITS = 8
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 203: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 211: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 217: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 203: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 211: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 217: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 203: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 211: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 217: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 211: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 217: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 228: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 228: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 228: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 228: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 228: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 228: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 228: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" line 228: Instantiating black box module <SRL16E>.
Entity <SRL_FIFO> analyzed. Unit <SRL_FIFO> generated.

Analyzing generic Entity <OPB_UARTLITE_TX> in library <opb_uartlite_v1_00_b> (Architecture <IMP>).
	C_DATA_BITS = 8
	C_ODD_PARITY = 0
	C_USE_PARITY = 0
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 249: Instantiating black box module <SRL16E>.
    Set user-defined property "INIT =  0001" for instance <DIV16_SRL16E> in unit <OPB_UARTLITE_TX>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 264: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 314: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 322: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 314: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 322: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 322: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 390: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 397: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" line 404: Instantiating black box module <MUXF6>.
Entity <OPB_UARTLITE_TX> analyzed. Unit <OPB_UARTLITE_TX> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <Baud_Rate>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/baudrate.vhd".
    Found 1-bit register for signal <EN_16x_Baud>.
    Found 10-bit down counter for signal <Count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <Baud_Rate> synthesized.


Synthesizing Unit <pselect>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd".
WARNING:Xst:647 - Input <A<16:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<4>> is never used or assigned.
Unit <pselect> synthesized.


Synthesizing Unit <SRL_FIFO>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd".
WARNING:Xst:1780 - Signal <addr_cy<4>> is never used or assigned.
    Found 1-bit xor2 for signal <$xor0005> created at line 199.
    Found 1-bit xor2 for signal <$xor0006> created at line 199.
    Found 1-bit xor2 for signal <$xor0007> created at line 199.
    Found 1-bit xor2 for signal <$xor0008> created at line 199.
    Found 1-bit register for signal <data_Exists_I>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <SRL_FIFO> synthesized.


Synthesizing Unit <OPB_UARTLITE_RX>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd".
WARNING:Xst:1305 - Output <RX_Parity_Error> is never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <parity> is never used or assigned.
WARNING:Xst:1780 - Signal <calc_Parity> is never used or assigned.
    Found 1-bit register for signal <FIFO_Write>.
    Found 1-bit register for signal <previous_RX>.
    Found 1-bit register for signal <running<0>>.
    Found 1-bit register for signal <rx_1>.
    Found 1-bit register for signal <rx_2>.
    Found 1-bit register for signal <start_Edge_Detected<0>>.
    Found 1-bit register for signal <stop_Bit_Position>.
    Summary:
	inferred   7 D-type flip-flop(s).
Unit <OPB_UARTLITE_RX> synthesized.


Synthesizing Unit <OPB_UARTLITE_TX>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd".
WARNING:Xst:1780 - Signal <parity> is never used or assigned.
WARNING:Xst:1780 - Signal <cnt_cy<0>> is never used or assigned.
WARNING:Xst:1780 - Signal <tx_Run1> is never used or assigned.
WARNING:Xst:1780 - Signal <calc_Parity> is never used or assigned.
    Found 1-bit register for signal <TX>.
    Found 1-bit register for signal <fifo_Read>.
    Found 3-bit register for signal <mux_sel>.
    Found 1-bit register for signal <serial_Data>.
    Found 1-bit register for signal <tx_DataBits>.
    Found 1-bit register for signal <tx_Start>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <OPB_UARTLITE_TX> synthesized.


Synthesizing Unit <OPB_UARTLITE_Core>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd".
WARNING:Xst:646 - Signal <rx_Parity_Error> is assigned but never used.
    Register <uart_CS_3> equivalent to <xfer_Ack> has been removed
    Found 1-bit register for signal <Interrupt>.
    Found 1-bit register for signal <enable_interrupts>.
    Found 1-bit register for signal <opb_RNW_1>.
    Found 1-bit register for signal <reset_RX_FIFO>.
    Found 1-bit register for signal <reset_TX_FIFO>.
    Found 1-bit register for signal <uart_CS_2>.
    Found 1-bit register for signal <xfer_Ack>.
    Summary:
	inferred   7 D-type flip-flop(s).
Unit <OPB_UARTLITE_Core> synthesized.


Synthesizing Unit <opb_uartlite>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite.vhd".
WARNING:Xst:647 - Input <OPB_BE> is never used.
WARNING:Xst:647 - Input <OPB_DBus<0:23>> is never used.
WARNING:Xst:647 - Input <OPB_seqAddr> is never used.
Unit <opb_uartlite> synthesized.


Synthesizing Unit <rs232_uart_1_wrapper>.
    Related source file is "C:/myproj2/firewall/myxps/hdl/rs232_uart_1_wrapper.vhd".
Unit <rs232_uart_1_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 10-bit down counter                                   : 1
# Registers                                            : 23
 1-bit register                                        : 22
 3-bit register                                        : 1
# Xors                                                 : 8
 1-bit xor2                                            : 8

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 10-bit down counter                                   : 1
# Registers                                            : 59
 Flip-Flops                                            : 59
# Xors                                                 : 8
 1-bit xor2                                            : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <rs232_uart_1_wrapper> ...

Optimizing unit <OPB_UARTLITE_TX> ...

Optimizing unit <OPB_UARTLITE_Core> ...

Optimizing unit <OPB_UARTLITE_RX> ...

Optimizing unit <SRL_FIFO> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

Processing Unit <rs232_uart_1_wrapper> :
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal <rs232_uart_1/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/rx_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.