rs232_uart_1_wrapper_xst.srp

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Release 8.2.02i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "rs232_uart_1_wrapper_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff896-7
Output File Name                   : "../implementation/rs232_uart_1_wrapper.ngc"

---- Source Options
Top Module Name                    : rs232_uart_1_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd" in Library opb_uartlite_v1_00_b.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/baudrate.vhd" in Library opb_uartlite_v1_00_b.
Entity <Baud_Rate> compiled.
Entity <Baud_Rate> (Architecture <VHDL_RTL>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" in Library opb_uartlite_v1_00_b.
Entity <OPB_UARTLITE_RX> compiled.
Entity <OPB_UARTLITE_RX> (Architecture <IMP>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd" in Library opb_uartlite_v1_00_b.
Entity <OPB_UARTLITE_TX> compiled.
Entity <OPB_UARTLITE_TX> (Architecture <IMP>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd" in Library common_v1_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" in Library opb_uartlite_v1_00_b.
Entity <OPB_UARTLITE_Core> compiled.
Entity <OPB_UARTLITE_Core> (Architecture <IMP>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite.vhd" in Library opb_uartlite_v1_00_b.
Entity <OPB_UARTLITE> compiled.
Entity <OPB_UARTLITE> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/myproj2/firewall/myxps/hdl/rs232_uart_1_wrapper.vhd" in Library work.
Entity <rs232_uart_1_wrapper> compiled.
Entity <rs232_uart_1_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <rs232_uart_1_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <opb_uartlite> in library <opb_uartlite_v1_00_b> (architecture <IMP>) with generics.
	C_BASEADDR = "01000000011000000000000000000000"
	C_BAUDRATE = 9600
	C_CLK_FREQ = 100000000
	C_DATA_BITS = 8
	C_HIGHADDR = "01000000011000001111111111111111"
	C_ODD_PARITY = 0
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_USE_PARITY = 0

Analyzing hierarchy for entity <pselect> in library <Common_v1_00_a> (architecture <imp>) with generics.
	C_AW = 32
	C_AB = 16
	C_BAR = "01000000011000000000000000000000"

Analyzing hierarchy for entity <OPB_UARTLITE_Core> in library <opb_uartlite_v1_00_b> (architecture <IMP>) with generics.
	C_BAUDRATE = 9600
	C_CLK_FREQ = 100000000
	C_DATA_BITS = 8
	C_ODD_PARITY = 0
	C_USE_PARITY = 0

Analyzing hierarchy for entity <Baud_Rate> in library <opb_uartlite_v1_00_b> (architecture <VHDL_RTL>) with generics.
	C_INACCURACY = 20
	C_RATIO = 651

Analyzing hierarchy for entity <OPB_UARTLITE_RX> in library <opb_uartlite_v1_00_b> (architecture <IMP>) with generics.
	C_DATA_BITS = 8
	C_ODD_PARITY = 0
	C_USE_PARITY = 0

Analyzing hierarchy for entity <OPB_UARTLITE_TX> in library <opb_uartlite_v1_00_b> (architecture <IMP>) with generics.
	C_USE_PARITY = 0
	C_DATA_BITS = 8
	C_ODD_PARITY = 0

Analyzing hierarchy for entity <SRL_FIFO> in library <opb_uartlite_v1_00_b> (architecture <IMP>) with generics.
	C_DATA_BITS = 8
	C_DEPTH = 16

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rs232_uart_1_wrapper> in library <work> (Architecture <STRUCTURE>).
    Set user-defined property "X_CORE_INFO =  opb_uartlite_v1_00_b" for unit <rs232_uart_1_wrapper>.
Entity <rs232_uart_1_wrapper> analyzed. Unit <rs232_uart_1_wrapper> generated.

Analyzing generic Entity <opb_uartlite> in library <opb_uartlite_v1_00_b> (Architecture <IMP>).
	C_OPB_AWIDTH = 32
	C_ODD_PARITY = 0
	C_DATA_BITS = 8
	C_BASEADDR = "01000000011000000000000000000000"
	C_CLK_FREQ = 100000000
	C_BAUDRATE = 9600
	C_USE_PARITY = 0
	C_OPB_DWIDTH = 32
	C_HIGHADDR = "01000000011000001111111111111111"
Entity <opb_uartlite> analyzed. Unit <opb_uartlite> generated.

Analyzing generic Entity <pselect> in library <Common_v1_00_a> (Architecture <imp>).
	C_BAR = "01000000011000000000000000000000"
	C_AW = 32
	C_AB = 16
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.
Entity <pselect> analyzed. Unit <pselect> generated.

Analyzing generic Entity <OPB_UARTLITE_Core> in library <opb_uartlite_v1_00_b> (Architecture <IMP>).
	C_USE_PARITY = 0
	C_ODD_PARITY = 0
	C_DATA_BITS = 8
	C_CLK_FREQ = 100000000
	C_BAUDRATE = 9600
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 241: Instantiating black box module <FDR>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 284: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 292: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 339: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 372: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 372: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 372: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 372: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 372: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 372: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 372: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd" line 372: Instantiating black box module <FDRE>.
Entity <OPB_UARTLITE_Core> analyzed. Unit <OPB_UARTLITE_Core> generated.

Analyzing generic Entity <Baud_Rate> in library <opb_uartlite_v1_00_b> (Architecture <VHDL_RTL>).
	C_RATIO = 651
	C_INACCURACY = 20
Entity <Baud_Rate> analyzed. Unit <Baud_Rate> generated.

Analyzing generic Entity <OPB_UARTLITE_RX> in library <opb_uartlite_v1_00_b> (Architecture <IMP>).
	C_DATA_BITS = 8
	C_ODD_PARITY = 0
	C_USE_PARITY = 0
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 279: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 299: Instantiating black box module <SRL16E>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 388: Instantiating black box module <FDSE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 402: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 402: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 402: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 402: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 402: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 402: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd" line 402: Instantiating black box module <FDRE>.
Entity <OPB_UARTLITE_RX> analyzed. Unit <OPB_UARTLITE_RX> generated.

Analyzing generic Entity <SRL_FIFO> in library <opb_uartlite_v1_00_b> (Architecture <IMP>).