plb2opb_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

    Found 2-bit register for signal <master_id_decode_i>.
    Found 2-bit register for signal <msize>.
    Found 30-bit adder for signal <opb_ABus_inc>.
    Found 30-bit register for signal <opb_ABus_reg>.
    Found 8-bit register for signal <opb_BE>.
    Found 1-bit register for signal <opb_RNW>.
    Found 1-bit register for signal <PLB_wrBurst_d1>.
    Found 64-bit register for signal <plb_wrDBus_d1>.
    Found 1-bit register for signal <plb_xfer_strobe_wr>.
    Found 1-bit register for signal <plb_xfer_strobe_wr_d1>.
    Found 1-bit register for signal <rcv_last_write_status>.
    Found 1-bit register for signal <rd_busy>.
    Found 4-bit register for signal <size>.
    Found 1-bit register for signal <start_flag_hold>.
    Found 1-bit register for signal <stop_rdburst_d1>.
    Found 1-bit register for signal <stop_wrburst_d1>.
    Found 1-bit register for signal <wr_active>.
    Found 1-bit register for signal <wr_busy>.
    Found 1-bit register for signal <wrBTerm_if_PAValid>.
    Found 1-bit register for signal <xfer_is_32>.
    Summary:
	inferred   7 ROM(s).
	inferred   1 Counter(s).
	inferred 216 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   5 Comparator(s).
	inferred   5 Multiplexer(s).
Unit <plb2opb_bridge_plb_if> synthesized.


Synthesizing Unit <plb2opb_bridge_rcv_data_if>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_rcv_data_if.vhd".
WARNING:Xst:1780 - Signal <srl_din> is never used or assigned.
WARNING:Xst:1780 - Signal <tflop_low_cntr> is never used or assigned.
WARNING:Xst:1780 - Signal <srl_val> is never used or assigned.
WARNING:Xst:1780 - Signal <opb_clk_en_async> is never used or assigned.
WARNING:Xst:1780 - Signal <tflop_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <srl_dout> is never used or assigned.
WARNING:Xst:1780 - Signal <tflop> is never used or assigned.
WARNING:Xst:1780 - Signal <tflop_period> is never used or assigned.
WARNING:Xst:1780 - Signal <opb_clk_en_sync> is never used or assigned.
    Found 1-bit register for signal <PLB_rcv_strobe>.
    Found 38-bit register for signal <PLB_rcv_data>.
    Summary:
	inferred  39 D-type flip-flop(s).
Unit <plb2opb_bridge_rcv_data_if> synthesized.


Synthesizing Unit <plb2opb_bridge>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge.vhd".
WARNING:Xst:647 - Input <DCR_Write> is never used.
WARNING:Xst:647 - Input <DCR_Read> is never used.
WARNING:Xst:647 - Input <DCR_DBus> is never used.
WARNING:Xst:647 - Input <DCR_ABus> is never used.
WARNING:Xst:646 - Signal <err_rd_wr_n> is assigned but never used.
WARNING:Xst:646 - Signal <PLB_PAValid_neg_edge> is assigned but never used.
WARNING:Xst:646 - Signal <master_id_decode> is assigned but never used.
WARNING:Xst:1780 - Signal <Block_on_OPB_tout_onRd> is never used or assigned.
WARNING:Xst:646 - Signal <lock_err> is assigned but never used.
WARNING:Xst:646 - Signal <err_addr> is assigned but never used.
WARNING:Xst:646 - Signal <BGO_SSize_int> is assigned but never used.
WARNING:Xst:646 - Signal <err_byte_enable> is assigned but never used.
    Found 2-bit register for signal <BGO_MBusy_int_1dly>.
    Found 2-bit register for signal <BGO_MBusy_int_2dly>.
    Found 2-bit register for signal <BGO_MErr_int_1dly>.
    Found 2-bit register for signal <BGO_MErr_int_2dly>.
    Found 1-bit register for signal <BGO_rdBTerm_int_1dly>.
    Found 1-bit register for signal <BGO_rdBTerm_int_2dly>.
    Found 1-bit register for signal <BGO_rdComp_int_1dly>.
    Found 1-bit register for signal <BGO_rdComp_int_2dly>.
    Found 1-bit register for signal <BGO_rdDAck_int_1dly>.
    Found 1-bit register for signal <BGO_rdDAck_int_2dly>.
    Found 64-bit register for signal <BGO_rdDBus_int_1dly>.
    Found 64-bit register for signal <BGO_rdDBus_int_2dly>.
    Found 4-bit register for signal <BGO_rdWdAddr_1dly>.
    Found 4-bit register for signal <BGO_rdWdAddr_2dly>.
    Found 1-bit register for signal <Block_on_Term_Rd_after_tout>.
    Found 1-bit register for signal <Block_on_Term_Rd_after_tout_EN>.
    Found 1-bit register for signal <Block_output_on_PLBabort_OPBside>.
    Found 1-bit register for signal <Block_output_on_PLBabort_regd>.
    Found 1-bit register for signal <Hold_Busy_til_Rearb_onOPBRetry>.
    Found 1-bit register for signal <PLB_RNW_and_PAValid_regd>.
    Found 1-bit register for signal <Read_inprog>.
    Found 1-bit register for signal <Wait_on_Rd>.
    Found 1-bit register for signal <Wait_on_Rd_2dly>.
    Summary:
	inferred 159 D-type flip-flop(s).
Unit <plb2opb_bridge> synthesized.


Synthesizing Unit <plb2opb_wrapper>.
    Related source file is "C:/myproj2/firewall/myxps/hdl/plb2opb_wrapper.vhd".
Unit <plb2opb_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 7
 4x1-bit ROM                                           : 5
 4x2-bit ROM                                           : 1
 8x1-bit ROM                                           : 1
# Adders/Subtractors                                   : 2
 30-bit adder                                          : 1
 4-bit adder                                           : 1
# Counters                                             : 4
 4-bit down counter                                    : 1
 4-bit up counter                                      : 2
 5-bit up counter                                      : 1
# Registers                                            : 167
 1-bit register                                        : 148
 2-bit register                                        : 7
 30-bit register                                       : 1
 32-bit register                                       : 1
 38-bit register                                       : 1
 4-bit register                                        : 5
 64-bit register                                       : 3
 8-bit register                                        : 1
# Comparators                                          : 6
 2-bit comparator equal                                : 1
 22-bit comparator equal                               : 1
 4-bit comparator greater                              : 1
 8-bit comparator equal                                : 2
 8-bit comparator not equal                            : 1
# Multiplexers                                         : 2
 1-bit 4-to-1 multiplexer                              : 1
 4-bit 4-to-1 multiplexer                              : 1
# Xors                                                 : 1
 1-bit xor2                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.
INFO:Xst:1647 - Data output of ROM <Mrom_brst_last_d> is tied to register <brst_last>.
INFO:Xst:2505 - HDL ADVISOR - Characteristics of this register prevent it from being combined with the ROM for implementation as read-only block RAM.
INFO:Xst:1647 - Data output of ROM <Mrom__mux0051> is tied to register <xfer_is_32>.
INFO:Xst:2506 - In order to maximize performance and save block RAM resources, this small ROM will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
INFO:Xst:1647 - Data output of ROM <Mrom__mux0052> is tied to register <at_1k_bndry>.
INFO:Xst:2506 - In order to maximize performance and save block RAM resources, this small ROM will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 7
 4x1-bit ROM                                           : 5
 4x2-bit ROM                                           : 1
 8x1-bit ROM                                           : 1
# Adders/Subtractors                                   : 2
 30-bit adder                                          : 1
 4-bit adder                                           : 1
# Counters                                             : 4
 4-bit down counter                                    : 1
 4-bit up counter                                      : 2
 5-bit up counter                                      : 1
# Registers                                            : 578
 Flip-Flops                                            : 578
# Comparators                                          : 6
 2-bit comparator equal                                : 1
 22-bit comparator equal                               : 1
 4-bit comparator greater                              : 1
 8-bit comparator equal                                : 2
 8-bit comparator not equal                            : 1
# Multiplexers                                         : 2
 1-bit 4-to-1 multiplexer                              : 1
 4-bit 4-to-1 multiplexer                              : 1
# Xors                                                 : 1
 1-bit xor2                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <plb2opb_brid