plb2opb_wrapper_xst.srp

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    Set user-defined property "INIT =  0000" for instance <DUALPORT_MEM_GEN[33].RAM_I> in unit <plb2opb_bridge_rcv_data_if_fifo>.
    Set user-defined property "INIT =  0000" for instance <DUALPORT_MEM_GEN[34].RAM_I> in unit <plb2opb_bridge_rcv_data_if_fifo>.
    Set user-defined property "INIT =  0000" for instance <DUALPORT_MEM_GEN[35].RAM_I> in unit <plb2opb_bridge_rcv_data_if_fifo>.
    Set user-defined property "INIT =  0000" for instance <DUALPORT_MEM_GEN[36].RAM_I> in unit <plb2opb_bridge_rcv_data_if_fifo>.
    Set user-defined property "INIT =  0000" for instance <DUALPORT_MEM_GEN[37].RAM_I> in unit <plb2opb_bridge_rcv_data_if_fifo>.
Entity <plb2opb_bridge_rcv_data_if_fifo> analyzed. Unit <plb2opb_bridge_rcv_data_if_fifo> generated.

Analyzing generic Entity <plb2opb_bridge_opb_if> in library <plb2opb_bridge_v1_01_a> (Architecture <plb2opb_bridge_opb_if>).
	C_BGI_TRANSABORT_CNT = 31
	C_BGI_TRANSABORT_CNT_WIDTH = 5
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_RCV_DATA_WIDTH = 38
	C_XFER_DATA_WIDTH = 72
    Set user-defined property "INIT =  0" for instance <OPB_XFER_PEND_FDRSE_I> in unit <plb2opb_bridge_opb_if>.
    Set user-defined property "INIT =  0" for instance <BGO_request_fdr> in unit <plb2opb_bridge_opb_if>.
    Set user-defined property "INIT =  0" for instance <BGO_select_fdrse> in unit <plb2opb_bridge_opb_if>.
Entity <plb2opb_bridge_opb_if> analyzed. Unit <plb2opb_bridge_opb_if> generated.

Analyzing generic Entity <plb2opb_interrupt> in library <plb2opb_bridge_v1_01_a> (Architecture <plb2opb_interrupt>).
	C_IRQ_ACTIVE = '1'
    Set user-defined property "INIT =  0" for instance <RISING_EDGE_GEN.INTERRUPT_REFF_I> in unit <plb2opb_interrupt>.
Entity <plb2opb_interrupt> analyzed. Unit <plb2opb_interrupt> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <or_gate>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate> synthesized.


Synthesizing Unit <mux_onehot>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <lutout> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
WARNING:Xst:646 - Signal <sel<0:21>> is assigned but never used.
WARNING:Xst:1780 - Signal <sel<22:43>> is never used or assigned.
WARNING:Xst:646 - Signal <Dreord<0:21>> is assigned but never used.
WARNING:Xst:1780 - Signal <Dreord<22:43>> is never used or assigned.
Unit <mux_onehot> synthesized.


Synthesizing Unit <plb2opb_bridge_xfer_if>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_xfer_if.vhd".
WARNING:Xst:1780 - Signal <bram_wr_addr> is never used or assigned.
WARNING:Xst:1780 - Signal <bram_rd_data> is never used or assigned.
WARNING:Xst:1780 - Signal <bram_rd_addr> is never used or assigned.
    Found 1-bit register for signal <OPB_xfer_abort_ack_d1>.
    Found 1-bit register for signal <OPB_xfer_abort_ack_d2>.
    Found 1-bit register for signal <OPB_xfer_abort_ack_d3>.
    Found 1-bit register for signal <OPB_xfer_start_ack_d1>.
    Found 1-bit register for signal <OPB_xfer_start_ack_d2>.
    Found 1-bit register for signal <OPB_xfer_start_ack_d3>.
    Found 1-bit register for signal <PLB_hold_buslock_d1>.
    Found 1-bit register for signal <PLB_hold_buslock_d2>.
    Found 1-bit register for signal <PLB_hold_buslock_d3>.
    Found 1-bit register for signal <PLB_xfer_abort_flag_d1>.
    Found 1-bit register for signal <PLB_xfer_abort_flag_d2>.
    Found 1-bit register for signal <PLB_xfer_abort_flag_d3>.
    Found 1-bit register for signal <PLB_xfer_start_flag_d1>.
    Found 1-bit register for signal <PLB_xfer_start_flag_d2>.
    Found 1-bit register for signal <PLB_xfer_start_flag_d3>.
    Found 4-bit up counter for signal <wr_addr>.
    Found 1-bit register for signal <wr_addr_rst>.
    Found 1-bit register for signal <wr_addr_rst_d1>.
    Summary:
	inferred   1 Counter(s).
	inferred  17 D-type flip-flop(s).
Unit <plb2opb_bridge_xfer_if> synthesized.


Synthesizing Unit <plb2opb_bridge_opb_if>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_opb_if.vhd".
    Register <Timeout_det> equivalent to <timeout_last> has been removed
    Found 1-bit register for signal <Err_rd_wr_n>.
    Found 1-bit register for signal <Err_ack_det>.
    Found 32-bit register for signal <Err_addr>.
    Found 4-bit register for signal <Err_byte_enable>.
    Found 1-bit register for signal <bgi_trans_abort_i>.
    Found 5-bit up counter for signal <bgi_transabort_cntr>.
    Found 1-bit register for signal <hold_buslock>.
    Found 1-bit register for signal <opb_xfer_start_flag_d1>.
    Found 1-bit register for signal <retry_last>.
    Found 1-bit register for signal <rst_d1>.
    Found 1-bit register for signal <rst_d2>.
    Found 1-bit register for signal <timeout_last>.
    Found 4-bit up counter for signal <xfer_rd_addr>.
    Found 4-bit adder for signal <xfer_rd_addr_inc>.
    Summary:
	inferred   2 Counter(s).
	inferred  45 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <plb2opb_bridge_opb_if> synthesized.


Synthesizing Unit <plb2opb_interrupt>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_interrupt.vhd".
Unit <plb2opb_interrupt> synthesized.


Synthesizing Unit <pselect>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd".
WARNING:Xst:647 - Input <A<1:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<1>> is never used or assigned.
Unit <pselect> synthesized.


Synthesizing Unit <plb2opb_bridge_srl16x30>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_srl16x30.vhd".
Unit <plb2opb_bridge_srl16x30> synthesized.


Synthesizing Unit <plb2opb_bridge_rcv_data_if_fifo>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_rcv_data_if_fifo.vhd".
    Found 2-bit comparator equal for signal <$cmp_eq0000> created at line 180.
    Found 2-bit register for signal <raddr>.
    Found 2-bit register for signal <waddr>.
    Found 2-bit register for signal <waddr_rclk_synced>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <plb2opb_bridge_rcv_data_if_fifo> synthesized.


Synthesizing Unit <plb2opb_bridge_plb_if>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_plb_if.vhd".
WARNING:Xst:647 - Input <PLB_wrPrim> is never used.
WARNING:Xst:647 - Input <PLB_ordered> is never used.
WARNING:Xst:647 - Input <PLB_compress> is never used.
WARNING:Xst:647 - Input <PLB_rdPrim> is never used.
WARNING:Xst:646 - Signal <PLB_wrBurst_d2> is assigned but never used.
WARNING:Xst:1780 - Signal <at_1k_bndry_next> is never used or assigned.
WARNING:Xst:1780 - Signal <byte_addr> is never used or assigned.
WARNING:Xst:646 - Signal <at_1k_guard_bndry_d1> is assigned but never used.
    Found 8x1-bit ROM for signal <brst_last_d>.
    Found 4x1-bit ROM for signal <at_1k_bndry_wrbterm>.
    Found 4x1-bit ROM for signal <brst_len1<0>>.
    Found 4x1-bit ROM for signal <brst_len1<1>>.
    Found 4x2-bit ROM for signal <$rom0000>.
    Found 4x1-bit ROM for signal <$mux0051>.
    Found 4x1-bit ROM for signal <$mux0052>.
    Found 64-bit register for signal <BGO_rdDBus>.
    Found 1-bit register for signal <PLB_hold_buslock>.
    Found 1-bit register for signal <Lock_err>.
    Found 4-bit register for signal <BGO_rdWdAddr>.
    Found 22-bit comparator equal for signal <$cmp_eq0002> created at line 1518.
    Found 8-bit comparator equal for signal <$cmp_eq0009> created at line 1562.
    Found 8-bit comparator equal for signal <$cmp_eq0010> created at line 1568.
    Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 1506.
    Found 8-bit comparator not equal for signal <$cmp_ne0006> created at line 1508.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0055>.
    Found 1-bit xor2 for signal <$xor0070> created at line 1542.
    Found 1-bit register for signal <abort_flag_hold>.
    Found 1-bit register for signal <access_valid>.
    Found 1-bit register for signal <access_valid_rearb>.
    Found 1-bit register for signal <addrAck_d1>.
    Found 1-bit register for signal <addrAck_d2>.
    Found 1-bit register for signal <at_1k_bndry>.
    Found 1-bit register for signal <at_1k_bndry_d1>.
    Found 1-bit register for signal <at_1k_bndry_d2>.
    Found 2-bit register for signal <BGO_MBusy_i>.
    Found 1-bit register for signal <BGO_rdComp_i>.
    Found 1-bit register for signal <BGO_rdDAck_i>.
    Found 1-bit register for signal <BGO_wrComp_i>.
    Found 1-bit register for signal <BGO_wrDAck_i>.
    Found 4-bit down counter for signal <brst_cnt>.
    Found 1-bit register for signal <brst_last>.
    Found 4-bit register for signal <brst_len>.
    Found 4-bit 4-to-1 multiplexer for signal <brst_len2>.
    Found 1-bit register for signal <busy>.
    Found 1-bit register for signal <end_of_wr_burst>.
    Found 1-bit register for signal <err_detect>.
    Found 1-bit register for signal <guarded_i>.