📄 plb2opb_wrapper_xst.srp
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Analyzing hierarchy for entity <pselect> in library <proc_common_v1_00_b> (architecture <imp>) with generics. C_AB = 1 C_AW = 32 C_BAR = "00000000000000000000000000000000"Analyzing hierarchy for entity <or_gate> in library <proc_common_v1_00_b> (architecture <imp>) with generics. C_BUS_WIDTH = 1 C_OR_WIDTH = 1 C_USE_LUT_OR = trueAnalyzing hierarchy for entity <mux_onehot> in library <proc_common_v1_00_b> (architecture <imp>) with generics. C_NB = 1 C_DW = 22Analyzing hierarchy for entity <plb2opb_bridge_srl16x30> in library <plb2opb_bridge_v1_01_a> (architecture <plb2opb_bridge_srl16x30>) with generics. C_DATA_WIDTH = 30Analyzing hierarchy for entity <plb2opb_bridge_rcv_data_if_fifo> in library <plb2opb_bridge_v1_01_a> (architecture <plb2opb_bridge_rcv_data_if_fifo>) with generics. C_DATA_WIDTH = 38Building hierarchy successfully finished.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <plb2opb_wrapper> in library <work> (Architecture <STRUCTURE>). Set user-defined property "X_CORE_INFO = plb2opb_bridge_v1_01_a" for unit <plb2opb_wrapper>. Set property "syn_maxfan = 10000" for signal <PLB_Clk> in unit <plb2opb_bridge>. Set property "syn_maxfan = 10000" for signal <OPB_Rst> in unit <plb2opb_bridge>. Set property "syn_maxfan = 10000" for signal <OPB_Clk> in unit <plb2opb_bridge>.Entity <plb2opb_wrapper> analyzed. Unit <plb2opb_wrapper> generated.Analyzing generic Entity <plb2opb_bridge> in library <plb2opb_bridge_v1_01_a> (Architecture <plb2opb_bridge>). C_RNG1_BASEADDR = "11111111111111111111111111111111" C_RNG1_HIGHADDR = "00000000000000000000000000000000" C_HIGH_SPEED = 1 C_INCLUDE_BGI_TRANSABORT = 1 C_DCR_INTFCE = 0 C_RNG3_HIGHADDR = "00000000000000000000000000000000" C_RNG3_BASEADDR = "11111111111111111111111111111111" C_RNG2_HIGHADDR = "00000000000000000000000000000000" C_RNG2_BASEADDR = "11111111111111111111111111111111" C_DCR_AWIDTH = 10 C_DCR_BASEADDR = "1111111111" C_DCR_DWIDTH = 32 C_CLK_ASYNC = 1 C_FAMILY = "virtex2p" C_IRQ_ACTIVE = '1' C_NO_PLB_BURST = 0 C_BGI_TRANSABORT_CNT = 31 C_DCR_HIGHADDR = "0000000000" C_PLB_DWIDTH = 64 C_PLB_AWIDTH = 32 C_RNG0_BASEADDR = "00000000000000000000000000000000" C_PLB_MID_WIDTH = 1 C_RNG0_HIGHADDR = "01111111111111111111111111111111" C_PLB_NUM_MASTERS = 2 C_NUM_ADDR_RNG = 1 C_OPB_AWIDTH = 32 C_OPB_DWIDTH = 32 Set property "syn_maxfan = 10000" for signal <PLB_Clk> in unit <plb2opb_bridge>. Set property "syn_maxfan = 10000" for signal <OPB_Rst> in unit <plb2opb_bridge>. Set property "syn_maxfan = 10000" for signal <OPB_Clk> in unit <plb2opb_bridge>.WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored. Set user-defined property "INIT = 8" for instance <I_PLB_RNW_and_PAValid> in unit <plb2opb_bridge>. Set user-defined property "INIT = 08F0" for instance <I_BGO_addrAck> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_Block_OPB_retry_onRd> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_Read_inprog_regd> in unit <plb2opb_bridge>. Set user-defined property "INIT = 4" for instance <I_Read_inprog_negedge> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_Read_inprog_negedge_Reg> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_Read_inprog_negedge_regd_OPBside_synch1> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_Read_inprog_negedge_regd_OPBside_synch2> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_Read_inprog_negedge_OPBside_1dly> in unit <plb2opb_bridge>. Set user-defined property "INIT = F2" for instance <I_OPBside_reset_Read_inprog_negedge_regd> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_A_side_Reg> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_OPB_retry_onRd_synch1> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_OPB_retry_onRd_synch2> in unit <plb2opb_bridge>. Set user-defined property "INIT = 1" for instance <I_B_Strobe_out_1dly> in unit <plb2opb_bridge>. Set user-defined property "INIT = F2" for instance <I_B_side_Reg_CLR> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_PLB_PAValid_1dly> in unit <plb2opb_bridge>. Set user-defined property "INIT = 4" for instance <I_PLB_PAValid_neg_edge> in unit <plb2opb_bridge>. Set user-defined property "INIT = F8" for instance <I_Block_output_on_PLBabort> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_OPB_timeout_Reg> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_OPB_timeout_onRd_synch1> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_OPB_timeout_onRd_synch2> in unit <plb2opb_bridge>. Set user-defined property "INIT = 1" for instance <I_OPB_timeout_Strobe_out_1dly> in unit <plb2opb_bridge>. Set user-defined property "INIT = F2" for instance <I_OPB_timeout_side_Reg_CLR> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_PLB_abort_Reg> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_PLB_abort_onRd_synch1> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_PLB_abort_onRd_synch2> in unit <plb2opb_bridge>. Set user-defined property "INIT = 1" for instance <I_PLB_abort_onRd_OPBside_1dly> in unit <plb2opb_bridge>. Set user-defined property "INIT = F2" for instance <I_PLB_abort_regd_clear> in unit <plb2opb_bridge>. Set user-defined property "INIT = 3200" for instance <I_OPB_rst_on_PLB_abort> in unit <plb2opb_bridge>. Set user-defined property "INIT = 0" for instance <I_BGO_select_regd> in unit <plb2opb_bridge>. Set user-defined property "INIT = 4" for instance <I_BGO_select_negedge> in unit <plb2opb_bridge>.Entity <plb2opb_bridge> analyzed. Unit <plb2opb_bridge> generated.Analyzing generic Entity <plb2opb_bridge_plb_if> in library <plb2opb_bridge_v1_01_a> (Architecture <plb2opb_bridge_plb_if>). C_PLB_AWIDTH = 32 C_NO_PLB_BURST = 0 C_RCV_DATA_WIDTH = 38 C_OPB_AWIDTH = 32 C_RNG1_BASEADDR = "11111111111111111111111111111111" C_RNG0_BASEADDR = "00000000000000000000000000000000" C_RNG0_HIGHADDR = "01111111111111111111111111111111" C_OPB_DWIDTH = 32 C_PLB_MID_WIDTH = 1 C_PLB_NUM_MASTERS = 2 C_NUM_ADDR_RNG = 1 C_PLB_DWIDTH = 64 C_RNG1_HIGHADDR = "00000000000000000000000000000000" C_RNG2_BASEADDR = "11111111111111111111111111111111" C_RNG2_HIGHADDR = "00000000000000000000000000000000" C_RNG3_BASEADDR = "11111111111111111111111111111111" C_RNG3_HIGHADDR = "00000000000000000000000000000000" C_XFER_DATA_WIDTH = 72Entity <plb2opb_bridge_plb_if> analyzed. Unit <plb2opb_bridge_plb_if> generated.Analyzing generic Entity <pselect> in library <proc_common_v1_00_b> (Architecture <imp>). C_BAR = "00000000000000000000000000000000" C_AW = 32 C_AB = 1WARNING:Xst:2211 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" line 195: Instantiating black box module <MUXCY>.Entity <pselect> analyzed. Unit <pselect> generated.Analyzing generic Entity <or_gate> in library <proc_common_v1_00_b> (Architecture <imp>). C_USE_LUT_OR = true C_OR_WIDTH = 1 C_BUS_WIDTH = 1Entity <or_gate> analyzed. Unit <or_gate> generated.Analyzing generic Entity <mux_onehot> in library <proc_common_v1_00_b> (Architecture <imp>). C_DW = 22 C_NB = 1Entity <mux_onehot> analyzed. Unit <mux_onehot> generated.Analyzing generic Entity <plb2opb_bridge_srl16x30> in library <plb2opb_bridge_v1_01_a> (Architecture <plb2opb_bridge_srl16x30>). C_DATA_WIDTH = 30 Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[0].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[1].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[2].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[3].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[4].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[5].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[6].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[7].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[8].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[9].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[10].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[11].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[12].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[13].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[14].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[15].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[16].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[17].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[18].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[19].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[20].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[21].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[22].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[23].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[24].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[25].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[26].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[27].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[28].SRL_I> in unit <plb2opb_bridge_srl16x30>. Set user-defined property "INIT = 0000" for instance <SRL_GENERATE[29].SRL_I> in unit <plb2opb_bridge_srl16x30>.Entity <plb2opb_bridge_srl16x30> analyzed. Unit <plb2opb_bridge_srl16x30> generated.Analyzing generic Entity <plb2opb_bridge_xfer_if> in library <plb2opb_bridge_v1_01_a> (Architecture <plb2opb_bridge_xfer_if>). C_CLK_ASYNC = 1 C_FAMILY = "virtex2p" C_HIGH_SPEED = 1 C_XFER_DATA_WIDTH = 72 C_XFER_RNW = 68 Set user-defined property "INIT = 0000" for instance <DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[0].DPRAM_I> in unit <plb2opb_bridge_xfer_if>. Set user-defined property "INIT = 0" for instance <DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[0].RAM_FF_I> in unit <plb2opb_bridge_xfer_if>. Set user-defined property "INIT = 0000" for instance <DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[1].DPRAM_I> in unit <plb2opb_bridge_xfer_if>. Set user-defined property "INIT = 0" for instance <DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[1].RAM_FF_I> in unit <plb2opb_bridge_xfer_if>. Set user-defined property "INIT = 0000" for instance <DUALPORT_RAM_GEN.RAM_FF_LOOP_GEN[2].DPRAM_I> in unit <plb2opb_bridge_xfer_if>.
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