plb2opb_wrapper_xst.srp

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Release 8.2.02i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "plb2opb_wrapper_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff896-7
Output File Name                   : "../implementation/plb2opb_wrapper.ngc"

---- Source Options
Top Module Name                    : plb2opb_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v1_00_b.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/family.vhd" in Library proc_common_v1_00_b.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" in Library proc_common_v1_00_b.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd" in Library proc_common_v1_00_b.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd" in Library proc_common_v1_00_b.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v1_00_b.
Package <proc_common_pkg> compiled.
WARNING:HDLParsers:3534 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" Line 364. In the function Get_RLOC_Name, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" Line 379. In the function Get_Reg_File_Area, not all control paths contain a return statement.
Package body <proc_common_pkg> compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_pkg.vhd" in Library plb2opb_bridge_v1_01_a.
Package <plb2opb_bridge_pkg> compiled.
Package body <plb2opb_bridge_pkg> compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_rcv_data_if_fifo.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_bridge_rcv_data_if_fifo> compiled.
Entity <plb2opb_bridge_rcv_data_if_fifo> (Architecture <plb2opb_bridge_rcv_data_if_fifo>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_srl16x30.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_bridge_srl16x30> compiled.
Entity <plb2opb_bridge_srl16x30> (Architecture <plb2opb_bridge_srl16x30>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_plb_if.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_bridge_plb_if> compiled.
Entity <plb2opb_bridge_plb_if> (Architecture <plb2opb_bridge_plb_if>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_xfer_if.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_bridge_xfer_if> compiled.
Entity <plb2opb_bridge_xfer_if> (Architecture <plb2opb_bridge_xfer_if>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_rcv_data_if.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_bridge_rcv_data_if> compiled.
Entity <plb2opb_bridge_rcv_data_if> (Architecture <plb2opb_bridge_rcv_data_if>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_opb_if.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_bridge_opb_if> compiled.
Entity <plb2opb_bridge_opb_if> (Architecture <plb2opb_bridge_opb_if>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_besr.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_bridge_besr> compiled.
Entity <plb2opb_bridge_besr> (Architecture <plb2opb_bridge_besr>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge_interrupt.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_interrupt> compiled.
Entity <plb2opb_interrupt> (Architecture <plb2opb_interrupt>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb2opb_bridge_v1_01_a/hdl/vhdl/plb2opb_bridge.vhd" in Library plb2opb_bridge_v1_01_a.
Entity <plb2opb_bridge> compiled.
Entity <plb2opb_bridge> (Architecture <plb2opb_bridge>) compiled.
Compiling vhdl file "C:/myproj2/firewall/myxps/hdl/plb2opb_wrapper.vhd" in Library work.
Entity <plb2opb_wrapper> compiled.
Entity <plb2opb_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <plb2opb_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <plb2opb_bridge> in library <plb2opb_bridge_v1_01_a> (architecture <plb2opb_bridge>) with generics.
	C_BGI_TRANSABORT_CNT = 31
	C_CLK_ASYNC = 1
	C_DCR_AWIDTH = 10
	C_DCR_BASEADDR = "1111111111"
	C_DCR_DWIDTH = 32
	C_DCR_HIGHADDR = "0000000000"
	C_DCR_INTFCE = 0
	C_FAMILY = "virtex2p"
	C_HIGH_SPEED = 1
	C_INCLUDE_BGI_TRANSABORT = 1
	C_IRQ_ACTIVE = '1'
	C_NO_PLB_BURST = 0
	C_NUM_ADDR_RNG = 1
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_PLB_AWIDTH = 32
	C_PLB_DWIDTH = 64
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_RNG0_BASEADDR = "00000000000000000000000000000000"
	C_RNG0_HIGHADDR = "01111111111111111111111111111111"
	C_RNG1_BASEADDR = "11111111111111111111111111111111"
	C_RNG1_HIGHADDR = "00000000000000000000000000000000"
	C_RNG2_BASEADDR = "11111111111111111111111111111111"
	C_RNG2_HIGHADDR = "00000000000000000000000000000000"
	C_RNG3_BASEADDR = "11111111111111111111111111111111"
	C_RNG3_HIGHADDR = "00000000000000000000000000000000"
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.

Analyzing hierarchy for entity <plb2opb_bridge_plb_if> in library <plb2opb_bridge_v1_01_a> (architecture <plb2opb_bridge_plb_if>) with generics.
	C_NO_PLB_BURST = 0
	C_NUM_ADDR_RNG = 1
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_PLB_AWIDTH = 32
	C_PLB_DWIDTH = 64
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_RCV_DATA_WIDTH = 38
	C_RNG0_BASEADDR = "00000000000000000000000000000000"
	C_RNG0_HIGHADDR = "01111111111111111111111111111111"
	C_RNG1_BASEADDR = "11111111111111111111111111111111"
	C_RNG1_HIGHADDR = "00000000000000000000000000000000"
	C_RNG2_BASEADDR = "11111111111111111111111111111111"
	C_RNG2_HIGHADDR = "00000000000000000000000000000000"
	C_RNG3_BASEADDR = "11111111111111111111111111111111"
	C_RNG3_HIGHADDR = "00000000000000000000000000000000"
	C_XFER_DATA_WIDTH = 72

Analyzing hierarchy for entity <plb2opb_bridge_xfer_if> in library <plb2opb_bridge_v1_01_a> (architecture <plb2opb_bridge_xfer_if>) with generics.
	C_XFER_DATA_WIDTH = 72
	C_FAMILY = "virtex2p"
	C_HIGH_SPEED = 1
	C_CLK_ASYNC = 1
	C_XFER_RNW = 68

Analyzing hierarchy for entity <plb2opb_bridge_rcv_data_if> in library <plb2opb_bridge_v1_01_a> (architecture <plb2opb_bridge_rcv_data_if>) with generics.
	C_CLK_ASYNC = 1
	C_RCV_DATA_WIDTH = 38

Analyzing hierarchy for entity <plb2opb_bridge_opb_if> in library <plb2opb_bridge_v1_01_a> (architecture <plb2opb_bridge_opb_if>) with generics.
	C_BGI_TRANSABORT_CNT_WIDTH = 5
	C_BGI_TRANSABORT_CNT = 31
	C_RCV_DATA_WIDTH = 38
	C_OPB_DWIDTH = 32
	C_XFER_DATA_WIDTH = 72
	C_OPB_AWIDTH = 32

Analyzing hierarchy for entity <plb2opb_interrupt> in library <plb2opb_bridge_v1_01_a> (architecture <plb2opb_interrupt>) with generics.
	C_IRQ_ACTIVE = '1'