plb_bram_if_cntlr_1_wrapper_xst.prj

本系统由服务器软件控制平台和fpga硬件处理系统组成

VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/family.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_gate.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/pselect.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/valid_be.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/down_counter.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/inferred_lut4.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/srl_fifo2.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/counter_bit.vhd
VHDL proc_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/counter.vhd
VHDL ipif_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\ipif_common_v1_00_b/hdl/vhdl/ipif_pkg.vhd
VHDL ipif_common_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\ipif_common_v1_00_b/hdl/vhdl/ipif_steer.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_counter_bit.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_counter.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_counter_top.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_occ_counter.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_occ_counter_top.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_adder_bit.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_adder.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_dpram_select.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/srl16_fifo.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/pf_dly1_mux.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/rdpfifo_dp_cntl.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/ipif_control_rd.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/rdpfifo_top.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/wrpfifo_dp_cntl.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/ipif_control_wr.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/wrpfifo_top.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/flex_addr_cntr.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/addr_reg_cntr_brst_flex.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/plb_address_decoder.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/burst_support.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/plb_slave_attachment_indet.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/plb_sesr_sear.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/plb_ipif_reset.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/plb_interrupt_control.vhd
VHDL plb_ipif_v1_00_e g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_ipif_v1_00_e/hdl/vhdl/plb_ipif.vhd
VHDL bram_if_cntlr_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\bram_if_cntlr_v1_00_b/hdl/vhdl/bram_if.vhd
VHDL plb_bram_if_cntlr_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\plb_bram_if_cntlr_v1_00_b/hdl/vhdl/plb_bram_if_cntlr.vhd
vhdl work ../hdl/plb_bram_if_cntlr_1_wrapper.vhd