plb_wrapper_xst.srp

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    Summary:
	inferred   2 D-type flip-flop(s).
Unit <plb_arbiter_logic> synthesized.


Synthesizing Unit <plb_v34>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_v34.vhd".
Unit <plb_v34> synthesized.


Synthesizing Unit <plb_wrapper>.
    Related source file is "C:/myproj2/firewall/myxps/hdl/plb_wrapper.vhd".
Unit <plb_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 3
 3-bit down counter                                    : 1
 4-bit down counter                                    : 2
# Registers                                            : 35
 1-bit register                                        : 26
 2-bit register                                        : 9
# Multiplexers                                         : 2
 1-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs> on signal <arbctrl_sm_cs[1:8]> with one-hot encoding.
----------------------
 State    | Encoding
----------------------
 00000001 | 00000001
 00001000 | 00000010
 01000000 | 00000100
 00000010 | 00001000
 00010000 | 00010000
 10000000 | 00100000
 00000100 | 01000000
 00100000 | 10000000
----------------------
Loading device for application Rf_Device from file '2vp30.nph' in environment g:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# Counters                                             : 3
 3-bit down counter                                    : 1
 4-bit down counter                                    : 2
# Registers                                            : 58
 Flip-Flops                                            : 58
# Multiplexers                                         : 2
 1-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <plb_wrapper> ...

Optimizing unit <priority_encoder> ...

Optimizing unit <or_gate_3> ...

Optimizing unit <mux_onehot_1> ...

Optimizing unit <pending_priority> ...

Optimizing unit <muxed_signals> ...

Optimizing unit <watchdog_timer> ...

Optimizing unit <arb_registers> ...

Optimizing unit <arb_control_sm> ...

Optimizing unit <mux_onehot_7> ...

Mapping all equations...
Building and optimizing final netlist ...
FlipFlop plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_0 has been replicated 2 time(s)
FlipFlop plb/I_PLB_ARBITER_LOGIC/I_PRIORITY_ENCODER/I_ARBADDRSEL/arbAddrSelReg_i_1 has been replicated 2 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 70
 Flip-Flops                                            : 70

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/plb_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 871

Cell Usage :
# BELS                             : 451
#      GND                         : 1
#      INV                         : 5
#      LUT2                        : 101
#      LUT2_D                      : 2
#      LUT3                        : 54
#      LUT3_D                      : 2
#      LUT3_L                      : 3
#      LUT4                        : 218
#      LUT4_D                      : 10
#      LUT4_L                      : 8
#      MUXCY                       : 44
#      MUXF5                       : 2
#      VCC                         : 1
# FlipFlops/Latches                : 70
#      FD                          : 1
#      FDR                         : 22
#      FDRE                        : 41
#      FDRS                        : 3
#      FDS                         : 3
# Shift Registers                  : 1
#      SRL16                       : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                     238  out of  13696     1%  
 Number of Slice Flip Flops:            70  out of  27392     0%  
 Number of 4 input LUTs:               404  out of  27392     1%  
    Number used as logic:              403
    Number used as Shift registers:      1
 Number of IOs:                        871
 Number of bonded IOBs:                  0  out of    556     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+-------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                       | Load  |
-----------------------------------+-------------------------------------------------------------+-------+
PLB_Clk                            | NONE(plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbDisMReqReg_1)| 71    |
-----------------------------------+-------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 4.495ns (Maximum Frequency: 222.450MHz)
   Minimum input arrival time before clock: 3.698ns
   Maximum output required time after clock: 3.680ns
   Maximum combinational path delay: 2.549ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'PLB_Clk'
  Clock period: 4.495ns (frequency: 222.450MHz)
  Total number of paths / destination ports: 1196 / 173
-------------------------------------------------------------------------
Delay:               4.495ns (Levels of Logic = 5)
  Source:            plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_TIMEOUT_CNTR_I/cnt_0 (FF)
  Destination:       plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1 (FF)
  Source Clock:      PLB_Clk rising
  Destination Clock: PLB_Clk rising

  Data Path: plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_TIMEOUT_CNTR_I/cnt_0 to plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   0.370   0.514  plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_TIMEOUT_CNTR_I/cnt_0 (plb/I_PLB_ARBITER_LOGIC/I_WDT/WDT_TIMEOUT_CNTR_I/cnt_0)
     LUT4:I0->O            9   0.275   0.517  plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtCountIsZero_i1 (plb/I_PLB_ARBITER_LOGIC/wdtCountIsZero)
     LUT4:I2->O           10   0.275   0.529  plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtAddrAck_i1 (plb/I_PLB_ARBITER_LOGIC/wdtAddrAck)
     LUT4:I2->O            4   0.275   0.431  plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/LoadSecWr11 (plb/I_PLB_ARBITER_LOGIC/recomputeWrBits)
     LUT4_L:I2->LO         1   0.275   0.118  plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/priWrEn39_SW0 (N596)
     LUT4:I2->O            2   0.275   0.378  plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/priWrEn41 (plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/priWrEn)
     FDRE:CE                   0.263          plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1
    ----------------------------------------
    Total                      4.495ns (2.008ns logic, 2.487ns route)
                                       (44.7% logic, 55.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'PLB_Clk'
  Total number of paths / destination ports: 1123 / 89
-------------------------------------------------------------------------
Offset:              3.698ns (Levels of Logic = 5)
  Source:            Sl_wait<0> (PAD)
  Destination:       plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1 (FF)
  Destination Clock: PLB_Clk rising

  Data Path: Sl_wait<0> to plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I0->O            1   0.275   0.467  plb/I_PLB_SLAVE_ORS/WAIT_OR/_or00001 (PLB_Swait)
     LUT4:I0->O           10   0.275   0.529  plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtAddrAck_i1 (plb/I_PLB_ARBITER_LOGIC/wdtAddrAck)
     LUT4:I2->O            4   0.275   0.431  plb/I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/LoadSecWr11 (plb/I_PLB_ARBITER_LOGIC/recomputeWrBits)
     LUT4_L:I2->LO         1   0.275   0.118  plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/priWrEn39_SW0 (N596)
     LUT4:I2->O            2   0.275   0.378  plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/priWrEn41 (plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/priWrEn)
     FDRE:CE                   0.263          plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1
    ----------------------------------------
    Total                      3.698ns (1.774ns logic, 1.924ns route)
                                       (48.0% logic, 52.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'PLB_Clk'
  Total number of paths / destination ports: 435 / 163
-------------------------------------------------------------------------
Offset:              3.680ns (Levels of Logic = 4)
  Source:            plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1 (FF)
  Destination:       PLB_MWrBTerm<0> (PAD)
  Source Clock:      PLB_Clk rising

  Data Path: plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1 to PLB_MWrBTerm<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            68   0.370   0.858  plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1 (plb/I_PLB_ARBITER_LOGIC/I_ARBREGISTERS/ArbPriWrMasterReg_1)
     LUT4:I0->O            1   0.275   0.468  plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/_and0000_SW0 (N257)
     LUT3:I0->O            1   0.275   0.467  plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/_and0000 (PLB_wrBurst)
     LUT4:I0->O            2   0.275   0.416  plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtWrBTerm_i1 (plb/I_PLB_ARBITER_LOGIC/wdtWrBTerm)
     LUT4:I3->O            0   0.275   0.000  plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/_and00081 (PLB_MWrBTerm<1>)
    ----------------------------------------
    Total                      3.680ns (1.470ns logic, 2.210ns route)
                                       (39.9% logic, 60.1% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 818 / 400
-------------------------------------------------------------------------
Delay:               2.549ns (Levels of Logic = 4)
  Source:            M_wrBurst<1> (PAD)
  Destination:       PLB_MWrBTerm<0> (PAD)

  Data Path: M_wrBurst<1> to PLB_MWrBTerm<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I1->O            1   0.275   0.468  plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/_and0000_SW0 (N257)
     LUT3:I0->O            1   0.275   0.467  plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/_and0000 (PLB_wrBurst)
     LUT4:I0->O            2   0.275   0.416  plb/I_PLB_ARBITER_LOGIC/I_WDT/wdtWrBTerm_i1 (plb/I_PLB_ARBITER_LOGIC/wdtWrBTerm)
     LUT4:I3->O            0   0.275   0.000  plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/_and00081 (PLB_MWrBTerm<1>)
    ----------------------------------------
    Total                      2.549ns (1.198ns logic, 1.351ns route)
                                       (47.0% logic, 53.0% route)

=========================================================================
CPU : 41.78 / 41.97 s | Elapsed : 42.00 / 42.00 s
 
--> 

Total memory usage is 229496 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  131 (   0 filtered)
Number of infos    :    3 (   0 filtered)