plb_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
Unit <mux_onehot_5> synthesized.


Synthesizing Unit <mux_onehot_6>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <lutout<2>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
Unit <mux_onehot_6> synthesized.


Synthesizing Unit <mux_onehot_7>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <lutout<2>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<5>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<8>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<11>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<14>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<17>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<20>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<23>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<26>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<29>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<32>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<35>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<38>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<41>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<44>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<47>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<50>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<53>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<56>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<59>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<62>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<65>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<68>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<71>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<74>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<77>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<80>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<83>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<86>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<89>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<92>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<95>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
Unit <mux_onehot_7> synthesized.


Synthesizing Unit <or_gate_1>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_1> synthesized.


Synthesizing Unit <or_gate_2>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_2> synthesized.


Synthesizing Unit <or_gate_3>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_3> synthesized.


Synthesizing Unit <or_gate_4>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate_4> synthesized.


Synthesizing Unit <arb_control_sm>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/arb_control_sm.vhd".
    Found finite state machine <FSM_0> for signal <arbctrl_sm_cs>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 35                                             |
    | Inputs             | 12                                             |
    | Outputs            | 7                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | Rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000001                                       |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit 4-to-1 multiplexer for signal <LoadSecRdPriReg>.
    Found 1-bit register for signal <SAValid>.
    Found 1-bit register for signal <PAValid>.
    Found 1-bit 4-to-1 multiplexer for signal <LoadSecRd>.
    Found 3-bit down counter for signal <Cnt_on_plb2opb_rearb>.
    Found 1-bit register for signal <Cnt_on_plb2opb_rearb_en>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   3 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <arb_control_sm> synthesized.


Synthesizing Unit <gen_qual_req>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/gen_qual_req.vhd".
Unit <gen_qual_req> synthesized.


Synthesizing Unit <bus_lock_sm>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/bus_lock_sm.vhd".
    Found 1-bit register for signal <plb_buslock_reg>.
    Found 1-bit register for signal <sm_buslock_reg>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <bus_lock_sm> synthesized.


Synthesizing Unit <arb_addr_sel>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/arb_addr_sel.vhd".
    Found 2-bit register for signal <arbAddrSelReg_i>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <arb_addr_sel> synthesized.


Synthesizing Unit <mux_onehot_8>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <lutout<2>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
Unit <mux_onehot_8> synthesized.


Synthesizing Unit <qual_request>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/qual_request.vhd".
Unit <qual_request> synthesized.


Synthesizing Unit <qual_priority>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/qual_priority.vhd".
Unit <qual_priority> synthesized.


Synthesizing Unit <or_bits_1>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_bits.vhd".
WARNING:Xst:647 - Input <In_bus<0:1>> is never used.
Unit <or_bits_1> synthesized.


Synthesizing Unit <or_bits_2>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_bits.vhd".
WARNING:Xst:647 - Input <In_bus<0>> is never used.
WARNING:Xst:647 - Input <In_bus<2:3>> is never used.
Unit <or_bits_2> synthesized.


Synthesizing Unit <or_bits_3>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_bits.vhd".
WARNING:Xst:647 - Input <In_bus<0:2>> is never used.
Unit <or_bits_3> synthesized.


Synthesizing Unit <bus_control>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/bus_control.vhd".
Unit <bus_control> synthesized.


Synthesizing Unit <down_counter>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/down_counter.vhd".
    Found 4-bit down counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
Unit <down_counter> synthesized.


Synthesizing Unit <plb_addrpath>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_addrpath.vhd".
Unit <plb_addrpath> synthesized.


Synthesizing Unit <plb_wr_datapath>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_wr_datapath.vhd".
WARNING:Xst:1780 - Signal <wr_dack> is never used or assigned.
Unit <plb_wr_datapath> synthesized.


Synthesizing Unit <plb_slave_ors>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_slave_ors.vhd".
Unit <plb_slave_ors> synthesized.


Synthesizing Unit <muxed_signals>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/muxed_signals.vhd".
WARNING:Xst:646 - Signal <plb_masterid_i<0>> is assigned but never used.
WARNING:Xst:653 - Signal <temp_or<0>> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <temp_or0<0>> is used but never assigned. Tied to value 0.
Unit <muxed_signals> synthesized.


Synthesizing Unit <arb_registers>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/arb_registers.vhd".
WARNING:Xst:1780 - Signal <arbPriWrBurstIn> is never used or assigned.
WARNING:Xst:1780 - Signal <arbSecWrBurstReg> is never used or assigned.
    Found 2-bit register for signal <ArbSecRdInProgPriorReg>.
    Found 1-bit register for signal <ArbPriRdBurstReg>.
    Found 2-bit register for signal <ArbPriRdMasterRegReg>.
    Found 2-bit register for signal <ArbDisMReqReg>.
    Found 2-bit register for signal <ArbPriWrMasterReg>.
    Found 2-bit register for signal <ArbSecWrInProgPriorReg>.
    Found 2-bit register for signal <arbPriRdMasterReg_i>.
    Found 1-bit register for signal <arbRdDBusBusyReg_i>.
    Found 1-bit register for signal <arbSecRdBurstReg>.
    Found 1-bit register for signal <arbSecRdInProgReg_i>.
    Found 2-bit register for signal <arbSecRdMasterReg_i>.
    Found 1-bit register for signal <arbSecWrInProgReg_i>.
    Found 2-bit register for signal <arbSecWrMasterReg_i>.
    Found 1-bit register for signal <arbWrDBusBusyReg_i>.
    Summary:
	inferred  22 D-type flip-flop(s).
Unit <arb_registers> synthesized.


Synthesizing Unit <watchdog_timer>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/watchdog_timer.vhd".
WARNING:Xst:1780 - Signal <wdtControlStatesG1> is never used or assigned.
WARNING:Xst:1780 - Signal <wdtTimeOutCountIn> is never used or assigned.
WARNING:Xst:1780 - Signal <wdtTransferSizeG1> is never used or assigned.
WARNING:Xst:1780 - Signal <wdtTimeOutG1> is never used or assigned.
    Found 1-bit register for signal <PLB_RNWReg>.
    Found 1-bit register for signal <PLB_RNWRegReg>.
    Found 1-bit register for signal <wdtBurstAccReg>.
    Found 1-bit register for signal <wdtCompReg>.
    Found 1-bit register for signal <wdtDAckReg>.
    Found 1-bit register for signal <wdtLine16AccReg>.
    Found 1-bit register for signal <wdtLine4AccReg>.
    Found 1-bit register for signal <wdtLine8AccReg>.
    Found 1-bit register for signal <wdtSingleAccReg>.
    Found 1-bit register for signal <wdtTimeOutReg_i>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <watchdog_timer> synthesized.


Synthesizing Unit <plb_interrupt>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_interrupt.vhd".
    Found 1-bit register for signal <sl_addrack_d1>.
    Found 1-bit register for signal <wdtaddrack_d1>.
    Found 1-bit register for signal <wdtcountiszero_d1>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <plb_interrupt> synthesized.


Synthesizing Unit <priority_encoder>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/priority_encoder.vhd".
WARNING:Xst:1780 - Signal <temp_sel> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 0.
Unit <priority_encoder> synthesized.


Synthesizing Unit <pending_priority>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/pending_priority.vhd".
WARNING:Xst:653 - Signal <one> is used but never assigned. Tied to value 1.
WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 0.
Unit <pending_priority> synthesized.


Synthesizing Unit <pend_request>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/pend_request.vhd".
WARNING:Xst:653 - Signal <one> is used but never assigned. Tied to value 1.
WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 0.
Unit <pend_request> synthesized.


Synthesizing Unit <plb_priority_encoder>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_priority_encoder.vhd".
WARNING:Xst:646 - Signal <avoid_map_error> is assigned but never used.
Unit <plb_priority_encoder> synthesized.


Synthesizing Unit <plb_arbiter_logic>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_arbiter_logic.vhd".
WARNING:Xst:647 - Input <DCR_Write> is never used.
WARNING:Xst:647 - Input <M_lockErr> is never used.
WARNING:Xst:647 - Input <PLB_BE> is never used.
WARNING:Xst:647 - Input <DCR_Read> is never used.
WARNING:Xst:647 - Input <DCR_ABus> is never used.
WARNING:Xst:647 - Input <PLB_ABus> is never used.
WARNING:Xst:647 - Input <PLB_type> is never used.
WARNING:Xst:646 - Signal <arbAValid> is assigned but never used.
WARNING:Xst:646 - Signal <wdtTimeOutAct> is assigned but never used.
WARNING:Xst:1780 - Signal <rdPrimReg> is never used or assigned.
WARNING:Xst:646 - Signal <wdtTimeOutReg> is assigned but never used.
WARNING:Xst:646 - Signal <arbSecWrMasterReg> is assigned but never used.
WARNING:Xst:646 - Signal <arbSecRdMasterReg> is assigned but never used.
    Found 1-bit register for signal <arbreset_i>.
    Found 1-bit register for signal <plb_rdprimreg_i>.