plb_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

	C_NUM_BITS = 1
	C_BUS_SIZE = 4
	C_START_BIT = 3

Analyzing hierarchy for entity <bus_control> in library <plb_v34_v1_02_a> (architecture <simulation>).

Analyzing hierarchy for entity <down_counter> in library <proc_common_v1_00_b> (architecture <simulation>) with generics.
	C_CNT_WIDTH = 4

Analyzing hierarchy for entity <qual_request> in library <plb_v34_v1_02_a> (architecture <simulation>).

Analyzing hierarchy for entity <qual_priority> in library <plb_v34_v1_02_a> (architecture <qual_priority>).

WARNING:Xst:2591 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_v34.vhd" line 732: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <plb_wrapper> in library <work> (Architecture <STRUCTURE>).
    Set user-defined property "X_CORE_INFO =  plb_v34_v1_02_a" for unit <plb_wrapper>.
    Set property "syn_maxfan = 10000" for signal <PLB_Rst> in unit <plb_v34>.
    Set property "syn_maxfan = 10000" for signal <PLB_Clk> in unit <plb_v34>.
Entity <plb_wrapper> analyzed. Unit <plb_wrapper> generated.

Analyzing generic Entity <plb_v34> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_BASEADDR = "1111111111"
	C_EXT_RESET_HIGH = 1
	C_DCR_INTFCE = 0
	C_PLB_AWIDTH = 32
	C_IRQ_ACTIVE = '1'
	C_DCR_DWIDTH = 32
	C_HIGHADDR = "0000000000"
	C_DCR_AWIDTH = 10
	C_NUM_OPBCLK_PLB2OPB_REARB = 5
	C_PLB_DWIDTH = 64
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_PLB_NUM_SLAVES = 2
    Set property "syn_maxfan = 10000" for signal <PLB_Rst> in unit <plb_v34>.
    Set property "syn_maxfan = 10000" for signal <PLB_Clk> in unit <plb_v34>.
    Set user-defined property "INIT =  FFFF" for instance <POR_SRL_I> in unit <plb_v34>.
    Set user-defined property "INIT =  1" for instance <POR_FF1_I> in unit <plb_v34>.
    Set user-defined property "INIT =  1" for instance <POR_FF2_I> in unit <plb_v34>.
Entity <plb_v34> analyzed. Unit <plb_v34> generated.

Analyzing generic Entity <plb_addrpath> in library <plb_v34_v1_02_a> (Architecture <implementation>).
	C_PLB_AWIDTH = 32
	C_NUM_MASTERS = 2
	C_PLB_DWIDTH = 64
Entity <plb_addrpath> analyzed. Unit <plb_addrpath> generated.

Analyzing generic Entity <mux_onehot.1> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_NB = 2
	C_DW = 32
Entity <mux_onehot.1> analyzed. Unit <mux_onehot.1> generated.

Analyzing generic Entity <mux_onehot.2> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_DW = 8
	C_NB = 2
Entity <mux_onehot.2> analyzed. Unit <mux_onehot.2> generated.

Analyzing generic Entity <mux_onehot.3> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_DW = 4
	C_NB = 2
Entity <mux_onehot.3> analyzed. Unit <mux_onehot.3> generated.

Analyzing generic Entity <mux_onehot.4> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_DW = 3
	C_NB = 2
Entity <mux_onehot.4> analyzed. Unit <mux_onehot.4> generated.

Analyzing generic Entity <mux_onehot.5> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_DW = 1
	C_NB = 2
Entity <mux_onehot.5> analyzed. Unit <mux_onehot.5> generated.

Analyzing generic Entity <mux_onehot.6> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_NB = 2
	C_DW = 2
Entity <mux_onehot.6> analyzed. Unit <mux_onehot.6> generated.

Analyzing generic Entity <plb_wr_datapath> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MASTERS = 2
	C_PLB_DWIDTH = 64
Entity <plb_wr_datapath> analyzed. Unit <plb_wr_datapath> generated.

Analyzing generic Entity <mux_onehot.7> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_NB = 2
	C_DW = 64
Entity <mux_onehot.7> analyzed. Unit <mux_onehot.7> generated.

Analyzing generic Entity <plb_rd_datapath> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MASTERS = 2
	C_PLB_DWIDTH = 64
Entity <plb_rd_datapath> analyzed. Unit <plb_rd_datapath> generated.

Analyzing generic Entity <plb_slave_ors> in library <plb_v34_v1_02_a> (Architecture <implementation>).
	C_NUM_MASTERS = 2
	C_NUM_SLAVES = 2
	C_PLB_DWIDTH = 64
Entity <plb_slave_ors> analyzed. Unit <plb_slave_ors> generated.

Analyzing generic Entity <or_gate.1> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_OR_WIDTH = 2
	C_BUS_WIDTH = 1
	C_USE_LUT_OR = true
Entity <or_gate.1> analyzed. Unit <or_gate.1> generated.

Analyzing generic Entity <or_gate.2> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_BUS_WIDTH = 2
	C_OR_WIDTH = 2
	C_USE_LUT_OR = true
Entity <or_gate.2> analyzed. Unit <or_gate.2> generated.

Analyzing generic Entity <or_gate.3> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_BUS_WIDTH = 64
	C_OR_WIDTH = 2
	C_USE_LUT_OR = true
Entity <or_gate.3> analyzed. Unit <or_gate.3> generated.

Analyzing generic Entity <or_gate.4> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_BUS_WIDTH = 4
	C_OR_WIDTH = 2
	C_USE_LUT_OR = true
Entity <or_gate.4> analyzed. Unit <or_gate.4> generated.

Analyzing generic Entity <plb_arbiter_logic> in library <plb_v34_v1_02_a> (Architecture <implementation>).
	C_BASEADDR = "1111111111"
	C_DCR_AWIDTH = 10
	C_DCR_DWIDTH = 32
	C_DCR_INTFCE = 0
	C_HIGHADDR = "0000000000"
	C_IRQ_ACTIVE = '1'
	C_MID_BITS = 1
	C_NUM_MASTERS = 2
	C_NUM_OPBCLK_PLB2OPB_REARB = 5
	C_NUM_PLB2OPB_BRIDGE = 2
	C_PLB_AWIDTH = 32
	C_PLB_DWIDTH = 64
Entity <plb_arbiter_logic> analyzed. Unit <plb_arbiter_logic> generated.

Analyzing generic Entity <plb_priority_encoder> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MSTRS_PAD = 4
	C_NUM_MASTERS = 2
    Set user-defined property "INIT =  1111" for instance <AVOID_MAPERR_GEN.AVOID_MAP_ERR_LUT> in unit <plb_priority_encoder>.
Entity <plb_priority_encoder> analyzed. Unit <plb_priority_encoder> generated.

Analyzing generic Entity <priority_encoder> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MASTERS = 4
Entity <priority_encoder> analyzed. Unit <priority_encoder> generated.

Analyzing Entity <qual_request> in library <plb_v34_v1_02_a> (Architecture <simulation>).
INFO:Xst:1561 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/qual_request.vhd" line 196: Mux is complete : default of case is discarded
Entity <qual_request> analyzed. Unit <qual_request> generated.

Analyzing generic Entity <pending_priority> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MASTERS = 2
Entity <pending_priority> analyzed. Unit <pending_priority> generated.

Analyzing Entity <qual_priority> in library <plb_v34_v1_02_a> (Architecture <qual_priority>).
INFO:Xst:1561 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/qual_priority.vhd" line 185: Mux is complete : default of case is discarded
Entity <qual_priority> analyzed. Unit <qual_priority> generated.

Analyzing generic Entity <pend_request> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MASTERS = 2
Entity <pend_request> analyzed. Unit <pend_request> generated.

Analyzing generic Entity <arb_addr_sel> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MASTERS = 2
Entity <arb_addr_sel> analyzed. Unit <arb_addr_sel> generated.

Analyzing generic Entity <mux_onehot.8> in library <proc_common_v1_00_b> (Architecture <imp>).
	C_DW = 2
	C_NB = 2
Entity <mux_onehot.8> analyzed. Unit <mux_onehot.8> generated.

Analyzing generic Entity <arb_control_sm> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_PLB2OPB_BRIDGE = 2
	C_NUM_OPBCLK_PLB2OPB_REARB = 5
	C_NUM_MASTERS = 2
Entity <arb_control_sm> analyzed. Unit <arb_control_sm> generated.

Analyzing generic Entity <gen_qual_req> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MASTERS = 2
Entity <gen_qual_req> analyzed. Unit <gen_qual_req> generated.

Analyzing generic Entity <muxed_signals> in library <plb_v34_v1_02_a> (Architecture <implementation>).
	C_NUM_MSTRS_PAD = 4
	C_NUM_MASTERS = 2
	C_MID_BITS = 1
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" line 243: VHDL Assertion Statement with non constant condition is ignored.
Entity <muxed_signals> analyzed. Unit <muxed_signals> generated.

Analyzing generic Entity <or_bits.1> in library <proc_common_v1_00_b> (Architecture <implementation>).
	C_START_BIT = 2
	C_BUS_SIZE = 4
	C_NUM_BITS = 2
Entity <or_bits.1> analyzed. Unit <or_bits.1> generated.

Analyzing generic Entity <or_bits.2> in library <proc_common_v1_00_b> (Architecture <implementation>).
	C_BUS_SIZE = 4
	C_NUM_BITS = 1
	C_START_BIT = 1
Entity <or_bits.2> analyzed. Unit <or_bits.2> generated.

Analyzing generic Entity <or_bits.3> in library <proc_common_v1_00_b> (Architecture <implementation>).
	C_BUS_SIZE = 4
	C_NUM_BITS = 1
	C_START_BIT = 3
Entity <or_bits.3> analyzed. Unit <or_bits.3> generated.

Analyzing generic Entity <arb_registers> in library <plb_v34_v1_02_a> (Architecture <simulation>).
	C_NUM_MASTERS = 2
Entity <arb_registers> analyzed. Unit <arb_registers> generated.

Analyzing Entity <bus_control> in library <plb_v34_v1_02_a> (Architecture <simulation>).
Entity <bus_control> analyzed. Unit <bus_control> generated.

Analyzing Entity <watchdog_timer> in library <plb_v34_v1_02_a> (Architecture <simulation>).
Entity <watchdog_timer> analyzed. Unit <watchdog_timer> generated.

Analyzing generic Entity <down_counter> in library <proc_common_v1_00_b> (Architecture <simulation>).
	C_CNT_WIDTH = 4
Entity <down_counter> analyzed. Unit <down_counter> generated.

Analyzing generic Entity <plb_interrupt> in library <plb_v34_v1_02_a> (Architecture <plb_interrupt>).
	C_IRQ_ACTIVE = '1'
    Set user-defined property "INIT =  0" for instance <RISING_EDGE_GEN.INTERRUPT_REFF_I> in unit <plb_interrupt>.
Entity <plb_interrupt> analyzed. Unit <plb_interrupt> generated.

Analyzing Entity <bus_lock_sm> in library <plb_v34_v1_02_a> (Architecture <implementation>).
Entity <bus_lock_sm> analyzed. Unit <bus_lock_sm> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <plb_rd_datapath>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_02_a/hdl/vhdl/plb_rd_datapath.vhd".
Unit <plb_rd_datapath> synthesized.


Synthesizing Unit <mux_onehot_1>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <lutout<2>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<5>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<8>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<11>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<14>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<17>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<20>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<23>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<26>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<29>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<32>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<35>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<38>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<41>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<44>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<47>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
Unit <mux_onehot_1> synthesized.


Synthesizing Unit <mux_onehot_2>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <lutout<2>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<5>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<8>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<11>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
Unit <mux_onehot_2> synthesized.


Synthesizing Unit <mux_onehot_3>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <lutout<2>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<5>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
Unit <mux_onehot_3> synthesized.


Synthesizing Unit <mux_onehot_4>.
    Related source file is "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd".
WARNING:Xst:1780 - Signal <lutout<2>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
Unit <mux_onehot_4> synthesized.


Synthesizing Unit <mux_onehot_5>.