dipsws_4bit_wrapper_xst.srp

本系统由服务器软件控制平台和fpga硬件处理系统组成

Release 8.2.02i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "dipsws_4bit_wrapper_xst.prj"

---- Target Parameters
Target Device                      : xc2vp30ff896-7
Output File Name                   : "../implementation/dipsws_4bit_wrapper.ngc"

---- Source Options
Top Module Name                    : dipsws_4bit_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd" in Library proc_common_v2_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd" in Library proc_common_v2_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd" in Library proc_common_v2_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd" in Library proc_common_v2_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd" in Library proc_common_v2_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v2_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v2_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd" in Library proc_common_v2_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd" in Library proc_common_v2_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd" in Library proc_common_v2_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v2_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd" in Library proc_common_v2_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd" in Library proc_common_v2_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd" in Library proc_common_v2_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd" in Library proc_common_v2_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v2_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd" in Library proc_common_v2_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd" in Library proc_common_v2_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd" in Library proc_common_v2_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd" in Library proc_common_v2_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd" in Library proc_common_v2_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd" in Library proc_common_v2_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd" in Library proc_common_v2_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v2_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd" in Library proc_common_v2_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd" in Library wrpfifo_v1_01_b.
Entity <pf_dly1_mux> compiled.
Entity <pf_dly1_mux> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd" in Library rdpfifo_v1_01_b.
Entity <ipif_control_rd> compiled.
Entity <ipif_control_rd> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd" in Library rdpfifo_v1_01_b.
Entity <rdpfifo_dp_cntl> compiled.
Entity <rdpfifo_dp_cntl> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd" in Library wrpfifo_v1_01_b.
Entity <ipif_control_wr> compiled.
Entity <ipif_control_wr> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd" in Library wrpfifo_v1_01_b.
Entity <wrpfifo_dp_cntl> compiled.
Entity <wrpfifo_dp_cntl> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_flex_addr_cntr.vhd" in Library opb_ipif_v3_01_a.
Entity <opb_flex_addr_cntr> compiled.
Entity <opb_flex_addr_cntr> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/srl_fifo3.vhd" in Library opb_ipif_v3_01_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/write_buffer.vhd" in Library opb_ipif_v3_01_a.
Entity <write_buffer> compiled.
Entity <write_buffer> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/reset_mir.vhd" in Library opb_ipif_v3_01_a.
Entity <reset_mir> compiled.
Entity <reset_mir> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/brst_addr_cntr.vhd" in Library opb_ipif_v3_01_a.
Entity <brst_addr_cntr> compiled.
Entity <brst_addr_cntr> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/brst_addr_cntr_reg.vhd" in Library opb_ipif_v3_01_a.
Entity <brst_addr_cntr_reg> compiled.
Entity <brst_addr_cntr_reg> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_be_gen.vhd" in Library opb_ipif_v3_01_a.
Entity <opb_be_gen> compiled.
Entity <opb_be_gen> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v1_00_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd" in Library wrpfifo_v1_01_b.
Entity <wrpfifo_top> compiled.
Entity <wrpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd" in Library rdpfifo_v1_01_b.
Entity <rdpfifo_top> compiled.
Entity <rdpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd" in Library opb_ipif_v3_01_a.
Entity <opb_bam> compiled.
Entity <opb_bam> (Architecture <implementation>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_ipif.vhd" in Library opb_ipif_v3_01_a.
Entity <opb_ipif> compiled.
Entity <opb_ipif> (Architecture <imp>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/gpio_core.vhd" in Library opb_gpio_v3_01_b.
Entity <GPIO_Core> compiled.
Entity <GPIO_Core> (Architecture <IMP>) compiled.
Compiling vhdl file "g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio.vhd" in Library opb_gpio_v3_01_b.
Entity <opb_gpio> compiled.
Entity <opb_gpio> (Architecture <imp>) compiled.
Compiling vhdl file "C:/myproj2/firewall/myxps/hdl/dipsws_4bit_wrapper.vhd" in Library work.
Entity <dipsws_4bit_wrapper> compiled.
Entity <dipsws_4bit_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <dipsws_4bit_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <opb_gpio> in library <opb_gpio_v3_01_b> (architecture <imp>) with generics.
	C_ALL_INPUTS = 1
	C_ALL_INPUTS_2 = 0
	C_BASEADDR = "01000000000000100000000000000000"